Apex 20K |
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Altera
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Using LVDS in APEX 20KE Devices |
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Original |
PDF
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Apex 20K |
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Altera
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AN 107: Using Altera Devices in Multi-Voltage Systems |
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Original |
PDF
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Apex 20K |
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Altera
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TB 56: Using APEX 20KE CAM for Fast Search Applications |
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Original |
PDF
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Apex 20K |
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Altera
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APEX 20KC Programmable Logic Device Data Sheet |
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Original |
PDF
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Apex 20K |
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Altera
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AN 106: Designing with 2.5-V Devices |
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Original |
PDF
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Apex 20K |
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Altera
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AN 138: LVDS Signaling Using APEX Devices I-O Pins |
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Original |
PDF
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Apex 20K |
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Altera
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AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices |
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Original |
PDF
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Apex 20K |
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Altera
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Using LVDS in the Quartus Software |
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Original |
PDF
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Apex 20K |
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Altera
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AN 117: Using Selectable I-O Standards in Altera Devices |
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Original |
PDF
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Apex 20K |
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Altera
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Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) |
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Original |
PDF
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Apex 20K |
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Altera
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TB 57: Power Consumption Comparison: APEX 20K vs. Virtex Devices |
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Original |
PDF
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Apex 20K |
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Altera
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APEX 20KE Programmable Logic Devices |
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Original |
PDF
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Apex 20K |
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Altera
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Board Design Guidelines for LVDS Systems |
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Original |
PDF
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Apex 20K |
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Altera
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TB 60: Advantages of APEX PLLs over Virtex DLLs |
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Original |
PDF
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Apex 20K |
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Altera
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AN 112: Integrating Product-Term Logic in APEX 20K Devices |
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Original |
PDF
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Apex 20K |
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Altera
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AN 114: Designing with FineLine BGA Packages |
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Original |
PDF
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Apex 20K |
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Altera
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Quartus Programmable Logic Development System & Software Data Sheet |
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Original |
PDF
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Apex 20K |
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Altera
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Configuration Devices for APEX & FLEX Devices Data Sheet |
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Original |
PDF
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Apex 20K |
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Altera
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EP20K400 Device |
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Original |
PDF
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Apex 20K |
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Altera
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MasterBlaster Serial-USB Communications Cable Data Sheet |
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Original |
PDF
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