Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    001AAD983 Search Results

    001AAD983 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74HCT25

    Abstract: No abstract text available
    Text: 74HC259; 74HCT259 8-bit addressable latch Rev. 5 — 7 August 2012 Product data sheet 1. General description The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL LSTTL . They are specified in compliance with JEDEC


    Original     		PDF 74HC259; 74HCT259 74HCT259 HCT259 74HCT25

    Untitled

    Abstract: No abstract text available
    Text: NSL001 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 1 — 19 November 2012 Product data sheet 1. General description The NSL001 is an 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks.


    Original     		PDF NSL001 NSL001

    74AHC3GU04

    Abstract: 74AHC3GU04DC 74AHC3GU04DP 74AHC3GU04GM JESD22-A114E MO-187
    Text: 74AHC3GU04 Inverter Rev. 03 — 26 January 2009 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the inverting single stage function. 2. Features • Symmetrical output impedance ■ High noise immunity


    Original     		PDF 74AHC3GU04 74AHC3GU04 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC3GU04DP 74AHC3GU04DC 74AHC3GU04DP 74AHC3GU04GM MO-187

    74AHC2G08

    Abstract: 74AHC2G08DC 74AHC2G08DP 74AHCT2G08 74AHCT2G08DC 74AHCT2G08DP JESD22-A114E
    Text: 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 03 — 12 January 2009 Product data sheet 1. General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2. Features • Symmetrical output impedance


    Original     		PDF 74AHC2G08; 74AHCT2G08 74AHCT2G08 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC2G08DP 74AHC2G08 74AHC2G08DC 74AHC2G08DP 74AHCT2G08DC 74AHCT2G08DP

    74HC3G04DP

    Abstract: 74HC3G04 74HC3G04DC 74HC3G04GD 74HCT3G04 74HCT3G04DC 74HCT3G04DP 74HCT3G04GD JESD22-A114E
    Text: 74HC3G04; 74HCT3G04 Inverter Rev. 03 — 2 July 2008 Product data sheet 1. General description The 74HC3G04 and 74HCT3G04 are high-speed Si-gate CMOS devices. They provide three inverting buffers. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.


    Original     		PDF 74HC3G04; 74HCT3G04 74HC3G04 74HCT3G04 JESD22-A114E JESD22-A115-A HCT3G04 74HC3G04DP 74HC3G04DC 74HC3G04GD 74HCT3G04DC 74HCT3G04DP 74HCT3G04GD

    74HC238

    Abstract: 74HCT238 DHVQFN16 EQUIVALENT 74HC238 SOT763-1 74HC238D 74HC238DB 74HC238N 74HC238PW JESD22-A114E
    Text: 74HC238; 74HCT238 3-to-8 line decoder/demultiplexer Rev. 03 — 16 July 2007 Product data sheet 1. General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL LSTTL . The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1,


    Original     		PDF 74HC238; 74HCT238 74HC238 74HCT238 74HC238/74HCT238 1-to-32 HCT238 DHVQFN16 EQUIVALENT 74HC238 SOT763-1 74HC238D 74HC238DB 74HC238N 74HC238PW JESD22-A114E

    74HC2G32

    Abstract: 74HC2G32DC 74HC2G32DP 74HCT2G32 74HCT2G32DC 74HCT2G32DP JESD22-A114E
    Text: 74HC2G32; 74HCT2G32 Dual 2-input OR gate Rev. 03 — 12 May 2009 Product data sheet 1. General description The 74HC2G32 and 74HCT2G32 are high-speed Si-gate CMOS devices. They provide two 2-input OR gates. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.


    Original     		PDF 74HC2G32; 74HCT2G32 74HC2G32 74HCT2G32 JESD22-A114E JESD22-A115-A HCT2G32 74HC2G32DC 74HC2G32DP 74HCT2G32DC 74HCT2G32DP

    VSSOP8

    Abstract: 74HC3GU04 74HC3GU04DC 74HC3GU04DP JESD22-A114E MO-187
    Text: 74HC3GU04 Inverter Rev. 03 — 11 May 2009 Product data sheet 1. General description The 74HC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. The 74HC3GU04 has CMOS input switching levels and supply voltage range 2 V to 6 V.


    Original     		PDF 74HC3GU04 74HC3GU04 JESD22-A114E JESD22-A115-A VSSOP8 74HC3GU04DC 74HC3GU04DP MO-187

    74AHC3G04

    Abstract: 74AHC3G04DC 74AHC3G04DP 74AHCT3G04 74AHCT3G04DC 74AHCT3G04DP JESD22-A114E
    Text: 74AHC3G04; 74AHCT3G04 Inverter Rev. 02 — 26 January 2009 Product data sheet 1. General description The 74AHC3G04; 74AHCT3G04 is a high-speed Si-gate CMOS device. The 74AHC3G04; 74AHCT3G04 provides three inverting buffers. 2. Features • Symmetrical output impedance


    Original     		PDF 74AHC3G04; 74AHCT3G04 74AHCT3G04 JESD22-A114E JESD22-A115-A JESD22-C101C 74AHC3G04DP 74AHC3G04 74AHC3G04DC 74AHC3G04DP 74AHCT3G04DC 74AHCT3G04DP

    74HC27

    Abstract: dhvqfn14 74HC27N 74HC27BQ 74HC27D 74HC27DB 74HC27PW 74HCT27 JESD22-A114E HCT273
    Text: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 03 — 7 January 2008 Product data sheet 1. General description The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL LSTTL . The 74HC27; 74HCT27 provides the 3-input NOR function.


    Original     		PDF 74HC27; 74HCT27 74HCT27 JESD22-A114E JESD22-A115-A 74HC27N DIP14 74HC27 dhvqfn14 74HC27N 74HC27BQ 74HC27D 74HC27DB 74HC27PW HCT273

    74HC

    Abstract: 74HC2G66 74HC2G66DC 74HC2G66DP 74HCT2G66 74HCT2G66DC 74HCT2G66DP JESD22-A114E
    Text: 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch Rev. 05 — 26 January 2009 Product data sheet 1. General description 74HC2G66 and 74HCT2G66 are high-speed Si-gate CMOS devices. They are dual single-pole single-throw analog switches. Each switch has two input/output pins


    Original     		PDF 74HC2G66; 74HCT2G66 74HC2G66 74HCT2G66 74HC2G66 JESD22-A114E HCT2G66 74HC 74HC2G66DC 74HC2G66DP 74HCT2G66DC 74HCT2G66DP

    74AHC373

    Abstract: 74AHC373D 74AHC373PW 74AHC573 74AHCT373 74AHCT373D 74AHCT573 AHCT373
    Text: 74AHC373; 74AHCT373 Octal D-type transparant latch; 3-state Rev. 03 — 20 May 2008 Product data sheet 1. General description The 74AHC373; 74AHCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard


    Original     		PDF 74AHC373; 74AHCT373 74AHCT373 AHCT373 74AHC373 74AHC373D 74AHC373PW 74AHC573 74AHCT373D 74AHCT573

    AHCT541

    Abstract: 74AHC541 74AHC541BQ 74AHC541D 74AHC541PW 74AHCT541 74AHCT541D 74AHCT541PW JESD22-A114E DHVQFN-20
    Text: 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state Rev. 03 — 12 November 2007 Product data sheet 1. General description The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device. The 74AHC541; 74AHCT541 are octal non-inverting buffer/line drivers with 3-state bus


    Original     		PDF 74AHC541; 74AHCT541 74AHCT541 74AHC541 JESD22-A114E 2000s AHCT541 74AHC541BQ 74AHC541D 74AHC541PW 74AHCT541D 74AHCT541PW DHVQFN-20

    74AHC595

    Abstract: 74AHC595D 74AHC595PW 74AHCT595 TSSOP16
    Text: 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches; 3-state Rev. 03 — 25 April 2008 Product data sheet 1. General description The 74AHC595; 74AHCT595 is a high-speed Si-gate CMOS device and is pin compatible


    Original     		PDF 74AHC595; 74AHCT595 74AHCT595 AHCT595 74AHC595 74AHC595D 74AHC595PW TSSOP16

    74HC123

    Abstract: 74HC123D 74hc123 application note 74hc123 application notes 74HCT123D 74HCT123N 74HCT423 74HC123N 74HC423 74HCT123
    Text: 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Rev. 6 — 14 March 2011 Product data sheet 1. General description The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL LSTTL . They are specified in compliance with JEDEC


    Original     		PDF 74HC123; 74HCT123 74HCT123 HCT123 74HC123 74HC123D 74hc123 application note 74hc123 application notes 74HCT123D 74HCT123N 74HCT423 74HC123N 74HC423

    74hct541

    Abstract: No abstract text available
    Text: 74HC541-Q100; 74HCT541-Q100 Octal buffer/line driver; 3-state Rev. 1 — 19 June 2014 Product data sheet 1. General description The 74HC541-Q100; 74HCT541-Q100 is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output-enables OE1 and OE2 . A HIGH on OEn


    Original     		PDF 74HC541-Q100; 74HCT541-Q100 74HCT541-Q100 AEC-Q100 HCT541 74hct541

    nxp ahct573

    Abstract: D191D 74AHC373 74AHC573 74AHC573D 74AHC573PW 74AHCT373 74AHCT573 ahct573
    Text: 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state Rev. 6 — 25 November 2010 Product data sheet 1. General description The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard


    Original     		PDF 74AHC573; 74AHCT573 74AHCT573 AHCT573 nxp ahct573 D191D 74AHC373 74AHC573 74AHC573D 74AHC573PW 74AHCT373 ahct573

    application johnson counter

    Abstract: 74HC4017BQ 74HCT4017BQ
    Text: 74HC4017-Q100; 74HCT4017-Q100 Johnson decade counter with 10 decoded outputs Rev. 1 — 24 March 2014 Product data sheet 1. General description The 74HC4017-Q100; 74HCT4017-Q100 is a 5-stage Johnson decade counter with 10 decoded outputs Q0 to Q9 . It has an output from the most significant flip-flop (Q5-9), two


    Original     		PDF 74HC4017-Q100; 74HCT4017-Q100 74HCT4017-Q100 HCT4017 application johnson counter 74HC4017BQ 74HCT4017BQ

    74HC541

    Abstract: 74HC541D/DG118
    Text: 74HC541; 74HTC541 Octal buffer/line driver; 3-state Rev. 3 — 15 April 2014 Product data sheet 1. General description The 74HC541; 74HCT541 is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables OE1 and OE2 . A HIGH on OEn causes the


    Original     		PDF 74HC541; 74HTC541 74HCT541 74HC541: 74HCT541: JESD22-A114F JESD22-A115-A HCT541 74HC541 74HC541D/DG118

    Untitled

    Abstract: No abstract text available
    Text: 74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 3 — 18 November 2013 Product data sheet 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q and Q


    Original     		PDF 74HC107; 74HCT107 74HCT107 HCT107

    74hc597

    Abstract: No abstract text available
    Text: 74HC597; 74HCT597 8-bit shift register with input flip-flops Rev. 3 — 15 April 2014 Product data sheet 1. General description The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage


    Original     		PDF 74HC597; 74HCT597 74HCT597 74HC597: 74HCT597: HCT597 74hc597

    74HC573

    Abstract: 74HC_HCT573 74HC573 20 PIN Current 74HCT573 74HC573 Logic Package Information 74HC573N 74HC573 Datasheet 74HC573-74HCT573 74HC573D 74HCT573D
    Text: 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Rev. 03 — 17 January 2006 Product data sheet 1. General description The 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type


    Original     		PDF 74HC573; 74HCT573 74HCT573 HCT573 74HC573 74HC_HCT573 74HC573 20 PIN Current 74HCT573 74HC573 Logic Package Information 74HC573N 74HC573 Datasheet 74HC573-74HCT573 74HC573D 74HCT573D

    74HC126 data sheet

    Abstract: 74HCT126 74HC126 74HC2G126 74HC2G126DC 74HC2G126DP 74HCT2G126 74HCT2G126DC 74HCT2G126DP
    Text: 74HC2G126; 74HCT2G126 Dual buffer/line driver; 3-state Rev. 02 — 15 December 2005 Product data sheet 1. General description The 74HC2G126; 74HCT2G126 is a high-speed Si-gate CMOS device. The 74HC2G126; 74HCT2G126 provides two non-inverting buffer/line drivers with 3-state


    Original     		PDF 74HC2G126; 74HCT2G126 74HCT2G126 74HC126 74HCT126. EIA/JESD22-A114-C HCT2G126 74HC126 data sheet 74HCT126 74HC2G126 74HC2G126DC 74HC2G126DP 74HCT2G126DC 74HCT2G126DP

    74HC_HCT138

    Abstract: 74HC138 data sheet 74HC138 EQUIVALENT 74HCT138 74HC138DB 74HC138N hct138d 74HC138 philips 74HCT138 74HC138PW
    Text: 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 03 — 23 December 2005 Product data sheet 1. General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1


    Original     		PDF 74HC138; 74HCT138 74HCT138 74HC_HCT138 74HC138 data sheet 74HC138 EQUIVALENT 74HCT138 74HC138DB 74HC138N hct138d 74HC138 philips 74HC138PW