Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    0X80000010 Search Results

    0X80000010 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    AT697

    Abstract: AT697F AT697E 4426D ASR16
    Text: Features • SPARC V8 High Performance Low-power 32-bit Architecture • • • • • • • • • • • • • • – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache


    Original
    32-bit 24-bit 33MHz 32/64-bit 4426D AT697 AT697F AT697E ASR16 PDF

    AMBA AXI to APB BUS Bridge verilog code

    Abstract: AMBA AXI 3 to APB BUS Bridge verilog code AMBA APB bus protocol PL341 state diagram of AMBA AXI protocol v 1.0 ARM DUI 0333
    Text: PrimeCell DDR2 Dynamic Memory Controller PL341 Revision: r0p0 Technical Reference Manual Copyright 2007 ARM Limited. All rights reserved. ARM DDI 0418A PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual Copyright © 2007 ARM Limited. All rights reserved.


    Original
    PL341) AMBA AXI to APB BUS Bridge verilog code AMBA AXI 3 to APB BUS Bridge verilog code AMBA APB bus protocol PL341 state diagram of AMBA AXI protocol v 1.0 ARM DUI 0333 PDF

    abb timer stt 17 s

    Abstract: FRB connector D03 ABB STT 111 manual abb timer stt 11 306122 abb timer stt 127 ML69Q6203 ML69Q6500 B69000 arm946 instruction
    Text: User’s Manual OKI A R M TM B A S E D M I C R O C O N T R O L L E R PRODUCTS ML696201/69Q6203 32-bit General Purpose Single-chip Microcontroller Revision 3.0 March 6, 2006 Preface This manual describes the hardware, software of the 32-bit microcontroller ML696201/69Q6203.


    Original
    ML696201/69Q6203 32-bit ML696201/69Q6203. ARM946E-S abb timer stt 17 s FRB connector D03 ABB STT 111 manual abb timer stt 11 306122 abb timer stt 127 ML69Q6203 ML69Q6500 B69000 arm946 instruction PDF

    SDRAM edac

    Abstract: AT697 Radiation report AT697 AT697E AT697F SPARC T4-2 at697e-2h-e MQFP256
    Text: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 32 KB 4-way associative Instruction Cache – 16 KB 2-way associative Data Cache


    Original
    32-bit 24-bit 33MHz 32/64-bit 4226H SDRAM edac AT697 Radiation report AT697 AT697E AT697F SPARC T4-2 at697e-2h-e MQFP256 PDF

    C3P47

    Abstract: LQFP144-P-2020-0 ML2110 ML2110TC OKI PRINTED CIRCUITS BOARD LTD date code C3P10 C3P38
    Text: OKI Semiconductor ML2110 FEDL2110-01 Issue Date: Mar. 25, 2002 Speech Control Processor GENERAL DESCRIPTION The ML2110 is a speech processor LSI device with internal D/A converter. It is optimized for text-to-speech synthesis. FEATURES • Parallel and serial interfaces


    Original
    ML2110 FEDL2110-01 ML2110 12bit 144-pin LQFP144-P-2020-0 ML2110TC) MFU32 C3P47 ML2110TC OKI PRINTED CIRCUITS BOARD LTD date code C3P10 C3P38 PDF

    MN103S

    Abstract: LIN source code MATSUSHITA PANASONIC printer motor message display on LED pic MN10300 MN103S00 PC-9800 PT103
    Text: MICROCOMPUTER MN10300 MN10300 Series C Source Code Debugger User’s Manual Pub.No.13130-022E PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. Sun, Sun OS, SPARC station2, and OpenWindows are registered trademarks of Sun Microsystems, Inc. USA .


    Original
    MN10300 MN10300 13130-022E MN103S LIN source code MATSUSHITA PANASONIC printer motor message display on LED pic MN103S00 PC-9800 PT103 PDF

    DIAB

    Abstract: smith trigger pic DSP56300 MPC8260 MPC860 MSC8101 RX30 SC140 0x4000000 VADS8260
    Text: Freescale Semiconductor, Inc. Application Note AN2269/D Rev 1, 3/2002 by Scott Smith and Renaud Le Friec CONTENTS RS-232 UTOPIA RJ45 PHY 100BaseT Flash MPC8260 60x SDRAM Buffer HDI16 MSC8101 HDI16 HDI16 MSC8101 HDI16 HDI16 MSC8101 HDI16 MSC8101 MSC8101 HDI16


    Original
    AN2269/D RS-232 100BaseT MPC8260 HDI16 MSC8101 DIAB smith trigger pic DSP56300 MPC8260 MPC860 MSC8101 RX30 SC140 0x4000000 VADS8260 PDF

    MSM7630

    Abstract: Y645 QFP100 rs1010 WT-117 wt004 16n256p immS12 4k20 rs008
    Text: J2F0005-29-12 ¡ 電子デバイス 作成:1999年 1月 MSM7630 l 前回作成:1998年 3月 MSM7630 汎用音声プロセッサ n 概要 MSM7630はDAコンバータを内蔵した音声用のプロセッサLSIです。テキスト音声変換などの音声


    Original
    J2F0005-29-12 MSM7630 MSM7630 MSM7630DALSI 40MHz26VAXMIPSROM/SRAM 100QFPQFP100-P-1420-0 65-BKMSM7630GS-BK A23-0 D31-16 Y645 QFP100 rs1010 WT-117 wt004 16n256p immS12 4k20 rs008 PDF

    fox 515 abb

    Abstract: AM29BX8 tqm860 FE1600 GPR circuit schematic diagram full MPC5200 schematic TQM860L ALL TYPE IC DATA AND manual substitution BOOK FE8700 LXT971ALE
    Text: Lite5200B User’s Manual Devices Supported: MPC5200B LITE5200BUM Rev. 0 10/2005 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road


    Original
    Lite5200B MPC5200B LITE5200BUM CH370 603-specific) fox 515 abb AM29BX8 tqm860 FE1600 GPR circuit schematic diagram full MPC5200 schematic TQM860L ALL TYPE IC DATA AND manual substitution BOOK FE8700 LXT971ALE PDF

    imx233

    Abstract: subwoofer amplifier diagram bose 64 x 128 lcd module pvg 2.1 subwoofer CIRCUIT DIAGRAM ram repair IMX23RM i.MX23 i.MX233 la 4508 ic pin diagram CCIR Report 549-3
    Text: i.MX23 Applications Processor Reference Manual IMX23RM Rev. 1 11/2009 Preliminary—Subject to Change Without Notice How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc.


    Original
    IMX23RM EL516 WMDRM10 imx233 subwoofer amplifier diagram bose 64 x 128 lcd module pvg 2.1 subwoofer CIRCUIT DIAGRAM ram repair IMX23RM i.MX23 i.MX233 la 4508 ic pin diagram CCIR Report 549-3 PDF

    tag 87

    Abstract: ATF697FF EB 203 D AT697 ATF280F AT697F PCI analogic device power 23MFLOPS ATF697FF-ZA-E 0x8000004C
    Text: ATF697FF Rad- hard 32 bit SPARC V8 Reconfigurable Processor DATASHEET Features • SPARC V8 High Performance Low-power 32-bit processor core • AT697F Sparc v8 processor • LEON2-FT 1.0.9.16.1 compliant • 8 Register Windows • Advanced Architecture 5 Stage Pipeline


    Original
    ATF697FF 32-bit AT697F 32/64-bit ATF280F tag 87 ATF697FF EB 203 D AT697 AT697F PCI analogic device power 23MFLOPS ATF697FF-ZA-E 0x8000004C PDF

    RY 227

    Abstract: ROUND ROBIN ARBITRATION AND FIXED PRIORITY "RY 227" at697f AT697F-KG-E 0722402VYC 5962-0722402vyc AT697 AT697F-2H-E ATC18RHA
    Text: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache – 32 kbyte Multi-sets Instruction Cache


    Original
    32-bit Two32-bit 32-bitTimer 33MHz 32/64-bit 7703D RY 227 ROUND ROBIN ARBITRATION AND FIXED PRIORITY "RY 227" at697f AT697F-KG-E 0722402VYC 5962-0722402vyc AT697 AT697F-2H-E ATC18RHA PDF

    Untitled

    Abstract: No abstract text available
    Text: Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual June 2004 Document Number: 252480-004 Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Contents INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS


    Original
    IXP42X IXC1100 IXC1100 PDF

    AMBA AXI verilog code

    Abstract: AMBA AXI to APB BUS Bridge verilog code state diagram of AMBA AXI protocol v 1.0 FD001 User Guide ARM DUI 0333 PL341 FD001 AMBA AXI specifications 0418C ARM DUI 0333
    Text: PrimeCell DDR2 Dynamic Memory Controller PL341 Revision: r0p1 Technical Reference Manual Copyright 2007 ARM Limited. All rights reserved. ARM DDI 0418C PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual Copyright © 2007 ARM Limited. All rights reserved.


    Original
    PL341) 0418C 32-bit AMBA AXI verilog code AMBA AXI to APB BUS Bridge verilog code state diagram of AMBA AXI protocol v 1.0 FD001 User Guide ARM DUI 0333 PL341 FD001 AMBA AXI specifications 0418C ARM DUI 0333 PDF

    DSP56300

    Abstract: MPC8260 MPC860 MSC8101 RX30 SC140
    Text: Application Note AN2269/D Rev 1, 3/2002 Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus by Scott Smith and Renaud Le Friec CONTENTS RS-232 UTOPIA RJ45 PHY 100BaseT Flash MPC8260 60x SDRAM Buffer MSC8101 HDI16 HDI16 MSC8101


    Original
    AN2269/D MPC8260 MSC8101 RS-232 100BaseT MPC8260 MSC8101 HDI16 DSP56300 MPC860 RX30 SC140 PDF

    at697f

    Abstract: QFP256 DIMENSION ISEL04 xor ttl 74 AT697F-KG-E 0X6C000000 QFP256 Package
    Text: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache – 32 kbyte Multi-sets Instruction Cache


    Original
    32-bit Two32-bit 32-bitTimer 33MHz 32/64-bit 7703C at697f QFP256 DIMENSION ISEL04 xor ttl 74 AT697F-KG-E 0X6C000000 QFP256 Package PDF

    msm7630

    Abstract: 0xF8000004 MSM7630GS-BK QFP100-P-1420-0 MSM7576 mc14573 0xF800001C 0xD0000000-0xDFFFFFFF circuit diagram of msm7630 MSM27C1602
    Text: DATA SHEET ¡ MSM7630 Universal Speech Processor SECOND EDITION ISSUE DATE : JAN. 1999 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information


    Original
    MSM7630 E2Y0002-29-11 QFP100-P-1420-0 65-BK msm7630 0xF8000004 MSM7630GS-BK MSM7576 mc14573 0xF800001C 0xD0000000-0xDFFFFFFF circuit diagram of msm7630 MSM27C1602 PDF

    Dynamic Memory Controller

    Abstract: AMBA AXI dma controller designer user guide verilog code for amba apb master PL340 edram macro AMBA AHB to APB BUS Bridge verilog code AMBA AXI designer user guide AMBA AXI to APB BUS Bridge verilog code FD001 User Guide ARM DUI 0333 0x00000212
    Text: PrimeCell Dynamic Memory Controller PL340 Revision: r2p0 Technical Reference Manual Copyright 2004-2007 ARM Limited. All rights reserved. ARM DDI 0331E PrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual Copyright © 2004-2007 ARM Limited. All rights reserved.


    Original
    PL340) 0331E Dynamic Memory Controller AMBA AXI dma controller designer user guide verilog code for amba apb master PL340 edram macro AMBA AHB to APB BUS Bridge verilog code AMBA AXI designer user guide AMBA AXI to APB BUS Bridge verilog code FD001 User Guide ARM DUI 0333 0x00000212 PDF

    RAMB16B

    Abstract: ramb16bwer XC6VLX240T-1FF 8 bit barrel shifter vhdl code verilog code for dual port ram with axi interface UG470
    Text: LogiCORE IP MicroBlaze Micro Controller System v1.1 DS865 April 24, 2012 Product Specification Introduction LogiCORE Facts The LogiCORE MicroBlaze™ Micro Controller System (MCS) is a complete standalone processor system intended for controller applications. It is highly


    Original
    DS865 RAMB16B ramb16bwer XC6VLX240T-1FF 8 bit barrel shifter vhdl code verilog code for dual port ram with axi interface UG470 PDF

    XTAL OSC 24

    Abstract: IMX* Sony ram repair FUSE CHIP, WHY SOC 1250 SONY philips 3h1 ferrite material subwoofer 1000 watts amplifier circuit subwoofer amplifier diagram bose pec 533 sine wave pwm circuit transistor su 110
    Text: i.MX23 Applications Processor Reference Manual IMX23RM Rev. 1 11/2009 Preliminary—Subject to Change Without Notice How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc.


    Original
    IMX23RM EL516 XTAL OSC 24 IMX* Sony ram repair FUSE CHIP, WHY SOC 1250 SONY philips 3h1 ferrite material subwoofer 1000 watts amplifier circuit subwoofer amplifier diagram bose pec 533 sine wave pwm circuit transistor su 110 PDF

    MICO32

    Abstract: design of dma controller using vhdl vhdl spi interface wishbone design of UART by using verilog flash controller verilog code lattice wrapper verilog with vhdl system design using pll vhdl code 8 BIT microprocessor design with verilog hdl code 16 byte register VERILOG spi flash controller
    Text: LatticeMico32 Migration Concerns Post ispLEVER 8.1 and Diamond 1.0 November 2010 Technical Note TN1221 Introduction The LatticeMico32 System Builder software provides a convenient user interface for building a microprocessorbased System on Chip SoC solution inside of Lattice FPGAs. Introduced in September 2006 it has provided a


    Original
    LatticeMico32 TN1221 LatticeMico32TM requeticeMico32 1-800-LATTICE MICO32 design of dma controller using vhdl vhdl spi interface wishbone design of UART by using verilog flash controller verilog code lattice wrapper verilog with vhdl system design using pll vhdl code 8 BIT microprocessor design with verilog hdl code 16 byte register VERILOG spi flash controller PDF

    KM428C257

    Abstract: bt 0240 adapter dell circuit diagram of motherboard xps YMF27 BtV2115 024c vcr Dell Dimension yamaha opl2 ymf 282 compaq 486 motherboard diagram
    Text: Advance Information Bt This document contains information on a product under development. The parametric information contains target parameters that are subject to change. BtV2115 MediaStream Controller Applications Related Products Distinguishing Features


    Original
    BtV2115 BtV2487 BtV2811A BtV2300 CLK17 CLK25 BtV2115 KM428C257 bt 0240 adapter dell circuit diagram of motherboard xps YMF27 024c vcr Dell Dimension yamaha opl2 ymf 282 compaq 486 motherboard diagram PDF

    DSP56300

    Abstract: MSC8101 MSC8101ADS RX30 SC140 RX2 1015
    Text: Application Note AN2244/D Rev 1, 2/2002 Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface by Renaud Le Friec and Scott Smith CONTENTS RS-232 UTOPIA RJ45 PHY 100BaseT HDI16 MSC8101 Flash 60x SDRAM Buffer MSC8101 HDI16 HDI16


    Original
    AN2244/D MSC8101ADS 60x-Compatible RS-232 100BaseT HDI16 MSC8101 DSP56300 MSC8101 RX30 SC140 RX2 1015 PDF

    bit310

    Abstract: MB86831 MB86832 MB86833 MB86834 XX10 0b00011 burst MB86930 332 TLE 3101 Fujitsu SPARC
    Text: FUJITSU SEMICONDUCTOR PM52-00004-1E PROCESSOR MANUAL SPARClite MB86830 HARDWARE MANUAL SPARClite MB86830 HARDWARE MANUAL FUJITSU LIMITED PREFACE • Purpose and intended audience The SPARClite family of 32-bit microcomputers conforms to the SPARC architecture that has


    Original
    PM52-00004-1E MB86830 32-bit bit310 MB86831 MB86832 MB86833 MB86834 XX10 0b00011 burst MB86930 332 TLE 3101 Fujitsu SPARC PDF