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    1-BIT D LATCH Search Results

    1-BIT D LATCH Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TCKE800NL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Latch, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    TCKE812NL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Latch, Fixed Over Voltage Clamp, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    TCKE712BNL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 13.2 V, 3.65 A, Latch, Adjustable Over Voltage Protection, WSON10 Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation

    1-BIT D LATCH Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    dimm pcb layout

    Abstract: No abstract text available
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit SN74SSTU32864GKER SN74SSTU32864 SCEM343, dimm pcb layout PDF

    A115-A

    Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER PDF

    D8-D25

    Abstract: No abstract text available
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit D8-D25 PDF

    A115-A

    Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit PDF

    A115-A

    Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit PDF

    A115-A

    Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit A115-A C101 SN74SSTU32864 SN74SSTU32864GKER PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer


    Original     		SN74SSTU32864 25-BIT SCES434 14-Bit PDF

    TMS664164

    Abstract: TMS664414 TMS664814
    Text: TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 D D D D D D D D D D D D Organization . . . 1 048 576 x 16 Bits x 4 Banks


    Original     		TMS664414, TMS664814, TMS664164 16-BIT SMOS695A x8/x16 125-MHz TMS664164 TMS664414 TMS664814 PDF

    TMS664164

    Abstract: TMS664414 TMS664814
    Text: TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 D D D D D D D D D D D D Organization . . . 1 048 576 x 16 Bits x 4 Banks


    Original     		TMS664414, TMS664814, TMS664164 16-BIT SMOS695A x8/x16 125-MHz TMS664164 TMS664414 TMS664814 PDF

    ADS1202

    Abstract: ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32 QFN32 5x5 package a4350
    Text: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs


    Original     		ADS1204 SBAS301A 10MHz, 16-Bit 14-Bit 10-Bit 12-Bit 20MHz QFN-32 ADS1202 ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32 QFN32 5x5 package a4350 PDF

    Untitled

    Abstract: No abstract text available
    Text: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs


    Original     		ADS1204 SBAS301A 10MHz, 16-Bit 14-Bit ADS1204 100dB 160kHz 10MHz. PDF

    ADS1202

    Abstract: ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32
    Text: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs


    Original     		ADS1204 SBAS301A 10MHz, 16-Bit 14-Bit 10-Bit 12-Bit 20MHz QFN-32 ADS1202 ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32 PDF

    Untitled

    Abstract: No abstract text available
    Text: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs


    Original     		ADS1204 SBAS301A 10MHz, 16-Bit 14-Bit ADS1204 100dB 160kHz 10MHz. PDF

    Untitled

    Abstract: No abstract text available
    Text: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs


    Original     		ADS1204 SBAS301A 10MHz, 16-Bit 14-Bit ADS1204 100dB 160kHz 10MHz. PDF

    QFN32 5x5 package

    Abstract: ADS1202 ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32 a4350
    Text: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs


    Original     		ADS1204 SBAS301A 10MHz, 16-Bit 14-Bit 10-Bit 12-Bit 20MHz QFN-32 QFN32 5x5 package ADS1202 ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32 a4350 PDF

    SMJ4C1024

    Abstract: 4c1024 SMJ44C256 4C1024-15 4c10248
    Text: SMJ4C1024 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 D D D D D D D D D D D D D Organization . . . 1 048 576 x 1-Bit Processed to MIL-STD-883, Class B Single 5-V Supply 10% Tolerance Performance Ranges:


    Original     		SMJ4C1024 SGMS023E MIL-STD-883, 4C1024-80 4C1024-10 4C1024-12 4C1024-15 SMJ4C1024 4c1024 SMJ44C256 4C1024-15 4c10248 PDF

    QFN32 5x5 package

    Abstract: opa 2064
    Text: ADS1204 SBAS301B − OCTOBER 2003 − REVISED AUGUST 2007 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal


    Original     		ADS1204 SBAS301B 10MHz, 16-Bit 14-Bit ADS1204 100dB 160kHz 10MHz. QFN32 5x5 package opa 2064 PDF

    Untitled

    Abstract: No abstract text available
    Text: IR3K01 8-Bit A /D Converter / IR3K01 • 8-Bit A/D Converter Pin Connections Description T he IR3K01 is a monolithic 8-bit A/D converter featuring an internal timer, V/F converter, counter and latch. f B IT 1 M S B ' D a ta ■ 1. 2. 3. 4. 5. 6. 7. 8. S ta r t


    OCR Scan     		IR3K01 IR3K01 28-pin PDF

    Untitled

    Abstract: No abstract text available
    Text: S M A « * ? H I 1 1 7 2 , C X D 1 1 7 2 6-Bit 20 MSPS Video A/D Converter CMOS February 1996 Features Description • R esolution. 6-Bit ± 1/2 LSB HI1172, CXD1172 is a 6-bit CMOS A/D converter for video


    OCR Scan     		HI1172, CXD1172 PDF

    Untitled

    Abstract: No abstract text available
    Text: D S 0 4 -1 3 2 0 1 -3 a E : DATASHEET : LINEAR 1C CMOS 8 BIT 4-CHANNEL MB86022 D/A CONVERTER CMOS 8-BIT 4-CHANNEL D/A CONVERTER The Fujitsu MB86022 is a 8-bit 4-channel Digital to Analog Converter which is fabricated with Fujitsu CMOS Technology. The data latch and output buffer circuitry


    OCR Scan     		MB86022 MB86022 DIP-24P-M03 FPT-24P-M02 I9502 G01Q3Ã PDF