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    Nexperia PMEG060V100EPDZ

    DIODE SCHOTTKY 60V 10A CFP15
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    DigiKey PMEG060V100EPDZ Reel 90,450 1,500
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    TME PMEG060V100EPDZ 2,156 1
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    Avnet Asia PMEG060V100EPDZ 8 Weeks 3,000
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    Chip Stock PMEG060V100EPDZ 22,053
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    EBV Elektronik PMEG060V100EPDZ 10 Weeks 1,500
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    IBS Electronics PMEG060V100EPDZ 1,500
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    New Advantage Corporation PMEG060V100EPDZ 57,000 1
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    FLIP ELECTRONICS MC100EP51MNR4G

    FLIP FLOP 1 ELEMENT D-TYPE 1 BIT
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    DigiKey MC100EP51MNR4G Reel 13,000 200
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    Nexperia PMEG060V100EPDAZ

    DIODE SCHOTTKY 60V 10A CFP15
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    DigiKey PMEG060V100EPDAZ Reel 5,000 5,000
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    Rochester Electronics PMEG060V100EPDAZ 115,000 1
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    TTI PMEG060V100EPDAZ Reel 15,000 5,000
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    TME PMEG060V100EPDAZ 1
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    Avnet Asia PMEG060V100EPDAZ 8 Weeks 5,000
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    EBV Elektronik PMEG060V100EPDAZ 10 Weeks 5,000
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    IBS Electronics PMEG060V100EPDAZ 5,000
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    FLIP ELECTRONICS MC100EP210SMNG

    IC CLK BUFFER 1:5 1GHZ 32QFN
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    DigiKey MC100EP210SMNG Tube 1,776 60
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    onsemi MC100EP56DTR2G

    IC DIFF DIG MULTPL 2X2:1 20TSSOP
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    DigiKey MC100EP56DTR2G Digi-Reel 1,581 1
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    MC100EP56DTR2G Cut Tape 1,581 1
    • 1 $12.78
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    MC100EP56DTR2G Digi-Reel 961 1
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    MC100EP56DTR2G Cut Tape 961 1
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    Rochester Electronics MC100EP56DTR2G 16,134 1
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    ComSIT USA MC100EP56DTR2G 2,128
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    Avnet Silica MC100EP56DTR2G 25 Weeks 2,500
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    EBV Elektronik MC100EP56DTR2G 26 Weeks 2,500
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    IBS Electronics MC100EP56DTR2G 2,500
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    100EP Datasheets Context Search

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    MC100EP90

    Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
    Text: MC10EP90, 100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.


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    MC10EP90, MC100EP90 MC10/100EP90 r14525 MC10EP90/D MC100EP90 MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2 PDF

    KEP05

    Abstract: HEP05 MC100EP05 MC10EP05
    Text: MC10EP05, 100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance


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    MC10EP05, MC100EP05 MC10/100EP05 LVEL05 LVEL05 r14525 MC10EP05/D KEP05 HEP05 MC100EP05 MC10EP05 PDF

    transistor k81

    Abstract: SY100EP33VKG SY100EP33VZC SY100EP33VZCTR SY10EP33VKC SY10EP33VKCTR SY10EP33VZC SY10EP33VZCTR EP-33
    Text: SY10EP33V/100EP33V 5V/3.3V, 4GHz, ÷4 PECL/LVPECL Divider Precision Edge General Description The SY10/100EP33V is an integrated ÷4 divider. The VBB pin, an internally-generated voltage supply, is ECL Pro available to this device only. For single-ended input


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    SY10EP33V/SY100EP33V SY10/100EP33V 460ps M9999-121010 transistor k81 SY100EP33VKG SY100EP33VZC SY100EP33VZCTR SY10EP33VKC SY10EP33VKCTR SY10EP33VZC SY10EP33VZCTR EP-33 PDF

    MC10EP016

    Abstract: MC100EP016 MC10E016
    Text: MC10EP016, 100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD


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    MC10EP016, MC100EP016 MC10/100EP016 MC10E016 MC10EP016/D MC10EP016 MC100EP016 PDF

    EP29

    Abstract: MC100EP29 MC10EP29
    Text: MC10EP29, 100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.


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    MC10EP29, MC100EP29 MC10/100EP29 MC10/100EL29. MC10EP29/D EP29 MC100EP29 MC10EP29 PDF

    MC100EP35

    Abstract: EL35 HP35 KP35 MC10EP35 code KP35
    Text: MC10EP35, 100EP35 3.3V / 5V ECL JK Flip−Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and


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    MC10EP35, MC100EP35 MC10/100EP35 HEP35 MC10EP35/D MC100EP35 EL35 HP35 KP35 MC10EP35 code KP35 PDF

    HEP58

    Abstract: MC100EP58 MC10EP58
    Text: MC10EP58, 100EP58 3.3V / 5VĄECL 2:1 Multiplexer The MC10/100EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices. The 100 Series contains temperature compensation. • 310 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical


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    MC10EP58, MC100EP58 MC10/100EP58 LVEL58 HEP58 KEP58 r14525 MC10EP58/D HEP58 MC100EP58 MC10EP58 PDF

    m 1305

    Abstract: MC10EP116 MC10EP116FA MC10EP116FAR2 D23011
    Text: MC10EP116 Hex Differential Line Receiver The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.


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    MC10EP116 MC10EP116/100EP116 r14525 MC10EP116/D m 1305 MC10EP116 MC10EP116FA MC10EP116FAR2 D23011 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10EP56, 100EP56 3.3V / 5V ECL Dual Differential 2:1 Multiplexer Description The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are


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    MC10EP56, MC100EP56 MC10/100EP56 MC10EP56/D PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10EP105, 100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,


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    MC10EP105, MC100EP105 MC10/100EP105 LVEL05 LVEL05 EP105 EP105 r14525 MC10EP105/D PDF

    Untitled

    Abstract: No abstract text available
    Text: MOTO RO LA °rderNumber:M R ro” Semiconductor Components M C 100EPT23 ♦ SO -8, D SUFFIX 8-LEAD PLASTIC SOIC PACKAGE CASE 751-06 ORDERING INFORMATION 100EPT23D Product Preview D ual D iffe re n tia l LVPECL to LVTTL T ra n s la to r SOIC PIN DESCRIPTION


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    100EPT23 MC100EPT23D 275MHz MC100EPT23/D PDF

    mux 8 inputs cmos

    Abstract: MUX CMOS 100EP SY89112U SY89850U SY89851U SY89852U SY89853U SY89854U SY89856U
    Text: Your 100EP PECL Logic Parts are Now Obsolete! Buffer & MUX Family Eliminates Stubs with Internal Termination All this from Micrel. And the Competition. RIP ◆ Internal Termination—No Stubs ◆ Directly Interface to AC- or DC-coupled Signals ◆ 2.5V and 3.3V Operation


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    100EP 10psp-p SY89850U SY89851U SY89852U SY89853U SY8959U SY8955U com/ad/sy8985x. mux 8 inputs cmos MUX CMOS SY89112U SY89850U SY89851U SY89852U SY89853U SY89854U SY89856U PDF

    EP57

    Abstract: MC100EP57 MC10EP57 100EP57
    Text: MC10EP57, 100EP57 3.3V / 5V ECL 4:1 Differential Multiplexer Description The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open pulled LOW via the input pulldown resistors the device can also be used as a differential 2:1 multiplexer


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    MC10EP57, MC100EP57 MC10/100EP57 MC10EP57/D EP57 MC100EP57 MC10EP57 100EP57 PDF

    EP105

    Abstract: MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2 marking CODE D2B
    Text: MC10EP105, 100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,


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    MC10EP105, MC100EP105 MC10/100EP105 LVEL05 LVEL05 EP105 EP105 r14525 MC10EP105/D MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2 marking CODE D2B PDF

    E131

    Abstract: MC100EP131 MC10EP131 QFN32 QFN32* socket
    Text: MC10EP131, 100EP131 3.3V / 5V ECL Quad D Flip−Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.


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    MC10EP131, MC100EP131 MC10/100EP131 EP131 MC10EP131/D E131 MC100EP131 MC10EP131 QFN32 QFN32* socket PDF

    MC100EP90

    Abstract: MC10EP90
    Text: MC10EP90, 100EP90 −3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.


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    MC10EP90, MC100EP90 MC10/100EP90 MC10EP90/D MC100EP90 MC10EP90 PDF

    EP105

    Abstract: MC100EP105 MC10EP105
    Text: MC10EP105, 100EP105 3.3V / 5V ECL Quad 2−Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,


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    MC10EP105, MC100EP105 MC10/100EP105 LVEL05 LVEL05 EP105 EP105 LQFP-32 MC10EP105/D MC100EP105 MC10EP105 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10EP90, 100EP90 -3.3V / -5V Triple ECL Input to LVPECL/PECL Output Translator Description The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.


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    MC10EP90, MC100EP90 MC10/100EP90 MC10EP90/D PDF

    MC100EP142

    Abstract: MC10EP142
    Text: MC10EP142, 100EP142 3.3V / 5V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in


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    MC10EP142, MC100EP142 MC10EP/100EP142 MC10/100EP142 MC10EP142/D MC100EP142 MC10EP142 PDF

    MC100EP139DTG

    Abstract: MC100EP139 MC10EP139 3815 dc
    Text: MC10EP139, 100EP139 3.3V / 5V ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common


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    MC10EP139, MC100EP139 MC10/100EP139 MC10EP139/D MC100EP139DTG MC100EP139 MC10EP139 3815 dc PDF

    Untitled

    Abstract: No abstract text available
    Text: MOTO RO LA °rderNumber:M RceI°„” Semiconductor Components M C 100EPT26 SO -8, D SUFFIX 8-LEAD PLASTIC SOIC PACKAGE CASE 751 ORDERING INFORMATION j D . J - rJ î i i 100EPT26D i r } - v j A vÎ SOIC V ü / Product Preview 1:2 F an o u t D iffe re n tia l


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    100EPT26 MC100EPT26D 275MHz MC100EPT26/D PDF

    Untitled

    Abstract: No abstract text available
    Text: MOTO RO LA °rder,tar5Jïïïï55S Semiconductor Components M C 100EP90 S O -2 0 , DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 9 48E O RDERING INFORMATION r . j - rJ k V -.v/ M 100EP90DT / i vj/ a 4 • *V . Product Preview PIN DESCRIPTION Triple LVECL to LVPECL


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    100EP90 C100EP90DT 350ps 20-Lead C100EP90/D PDF

    MC10EP01

    Abstract: No abstract text available
    Text: MC10EP016, 100EP016 3.3V / 5VĄECL 8-Bit Synchronous Binary Up Counter The MC10/100EP016 is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD


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    MC10EP016, MC100EP016 MC10/100EP016 MC10E016 r14525 MC10EP016/D MC10EP01 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10EP57, 100EP57 3.3V / 5V ECL 4:1 Differential Multiplexer Description The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open pulled LOW via the input pulldown resistors the device can also be used as a differential 2:1 multiplexer


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    MC10EP57, MC100EP57 MC10/100EP57 MC10EP57/D PDF