SUM110N04-04
Abstract: No abstract text available
Text: SPICE Device Model SUM110N04-04 Vishay Siliconix N-Channel 40-V D-S , 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Model Subcircuit) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range
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SUM110N04-04
0-to-10V
20-Mar-03
SUM110N04-04
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74168
Abstract: data sheet 74168 Si4910DY
Text: SPICE Device Model Si4910DY Vishay Siliconix N-Channel 40-V D-S MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range
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Si4910DY
S-60411Rev.
20-Mar-06
74168
data sheet 74168
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SUM110N04-04
Abstract: No abstract text available
Text: SPICE Device Model SUM110N04-04 Vishay Siliconix N-Channel 40-V D-S , 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range
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SUM110N04-04
capaci33
S-62312Rev.
27-Nov-06
SUM110N04-04
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74168
Abstract: data sheet 74168 Si4910DY
Text: SPICE Device Model Si4910DY Vishay Siliconix N-Channel 40-V D-S MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range
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Si4910DY
18-Jul-08
74168
data sheet 74168
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SUM110N04-04
Abstract: No abstract text available
Text: SPICE Device Model SUM110N04-04 Vishay Siliconix N-Channel 40-V D-S , 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range
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SUM110N04-04
18-Jul-08
SUM110N04-04
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Si4186DY
Abstract: si41 si4186
Text: SPICE Device Model Si4186DY Vishay Siliconix N-Channel 20 V D-S MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C
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Si4186DY
18-Jul-08
si41
si4186
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Untitled
Abstract: No abstract text available
Text: SPICE Device Model Si4186DY www.vishay.com Vishay Siliconix N-Channel 20 V D-S MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C
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Si4186DY
2002/95/EC.
2002/95/EC
2011/65/EU.
JS709A
02-Oct-12
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Untitled
Abstract: No abstract text available
Text: MC100EL59 5V ECL Triple 2:1 Multiplexer The MC100EL59 is a triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random
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MC100EL59
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
AN1568
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KVL01
Abstract: No abstract text available
Text: MC100LVEL01 3.3V ECL 4−Input OR/NOR The MC100LVEL01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in
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MC100LVEL01
LVEL01
KVL01
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
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KV58
Abstract: No abstract text available
Text: MC100LVEL58 3.3V ECL 2:1 Multiplexer The MC100LVEL58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and works from a 3.3 V supply. With AC performance similar to the EL58 device, the LVEL58 is ideal for low voltage applications which require the ultimate in AC
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MC100LVEL58
LVEL58
KVL58
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
KV58
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Untitled
Abstract: No abstract text available
Text: MC100LVEL59 3.3V ECL Triple 2:1 Multiplexer The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device
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MC100LVEL59
100LVEL59
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
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transistor BD 2420
Abstract: MARKING QB
Text: MC100LVEL12 3.3V ECL Low Impedance Driver The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply.
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MC100LVEL12
LVEL12
KVL12
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
transistor BD 2420
MARKING QB
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transistor BD 2420
Abstract: KVL31
Text: MC100LVEL31 3.3V ECL D Flip-Flop with Set and Reset The MC100LVEL31 is a D flip-flop with set and reset. The device is functionally equivalent to the EL31 device but operates from a 3.3 V supply. With propagation delays and output transition times essentially
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MC100LVEL31
LVEL31
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
transistor BD 2420
KVL31
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100LVEL13
Abstract: marking code QB
Text: MC100LVEL13 3.3V ECL Dual 1:3 Fanout Buffer The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer. The Low Output−Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device
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MC100LVEL13
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
AN1568
100LVEL13
marking code QB
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KVL05
Abstract: ECL IC NAND EL05
Text: MC100LVEL05 3.3V ECL 2-Input Differential AND/NAND The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally
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MC100LVEL05
MC100EL05
LVEL05
AND8020
AN1404
AN1405
AN1406
AN1503
KVL05
ECL IC NAND
EL05
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LQFP 128 pin Socket
Abstract: lqfp 7x7 tray
Text: MC100LVE164 3.3V ECL 16:1 Multiplexer The MC100LVE164 is a 16:1 multiplexer with a differential output. The select inputs SEL0, 1, 2, 3 control which one of the sixteen data inputs (A0 − A15) is propragated to the output. The device is functionally equivalent to the MC100E164 except it operates from a 3.3 V supply. The
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MC100LVE164
MC100E164
32-lead
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
LQFP 128 pin Socket
lqfp 7x7 tray
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HEL01
Abstract: transistor E101 KEL01
Text: MC10EL01, MC100EL01 5V ECL 4-Input OR/NOR The MC10EL/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101, the EL01 is ideally suited for those
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MC10EL01,
MC100EL01
MC10EL/100EL01
HEL01
KEL01
AND8020
AN1404
AN1405
AN1406
AN1503
transistor E101
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KVL16
Abstract: 1745 so8
Text: MC100LVEL16 3.3V ECL Differential Receiver The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a 3.3 V supply. The LVEL16 exhibits a wider VIHCMR range than its EL16 counterpart. With output transition times and propagation delays
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MC100LVEL16
LVEL16
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
KVL16
1745 so8
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100LVEL37
Abstract: No abstract text available
Text: MC100LVEL37 3.3V ECL 1:4 ÷1/÷2 Clock Fanout Buffer The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device offers two outputs at ÷1 of the input frequency, and two outputs at ÷2 of the input frequency. The Low Output−Output Skew of the
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MC100LVEL37
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
AN1568
100LVEL37
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KVL33
Abstract: KV33
Text: MC100LVEL33 3.3V ECL ÷4 Divider The MC100LVEL33 is an integrated ÷4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the
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MC100LVEL33
LVEL33
o8020
MC100LVEL33
AN1404
AN1405
AN1406
AN1503
AN1504
KVL33
KV33
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smd marking d2d
Abstract: No abstract text available
Text: 100304 Low Power Quint AND/NAND Gate General Description The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate outputs. All inputs have 50 kΩ pull-down resistors. n n n n n Features 2000V ESD protection Pin/function compatible with 100104
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DS100304-1
5962-9153701VXA
100304J-QMLV
100304WQMLV
5962-9153701VYA
1-Sep-2000]
smd marking d2d
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Untitled
Abstract: No abstract text available
Text: 100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-OR/NOR gate. The Function output is the wire-OR of all five exclusive-OR outputs. All inputs have 50 kΩ pull-down resistors. n n n n n Features 2000V ESD protection
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Out7000
100307DMQB
9459001MX
5962Full
9459001MYA
5962Cerdip
9459001VXA
100307J
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100LVEL17
Abstract: SO20L
Text: MC100LVEL17 3.3V ECL Quad Differential Receiver The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a −3.3 V or +3.3 V supply voltage. Under open input conditions, the D input will be biased at VCC/2
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MC100LVEL17
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
AN1568
100LVEL17
SO20L
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100LVEL40
Abstract: No abstract text available
Text: MC100LVEL40 3.3/5V ECL Differential Phase−Frequency Detector The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design
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MC100LVEL40
AND8020
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
AN1568
100LVEL40
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