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    Bourns Inc SRR4028-2R2Y

    Power Inductors - SMD 2.2uH 30% SMD 4028
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    TTI SRR4028-2R2Y Reel 22,000 500
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    Chip 1 Exchange HC-49-U-10.111MHZ 1,000
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    111MHZ Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET 256M bits SDRAM Bare Chip ECS2532EECN-A 8M words x 32 bits Features • Density: 256M bits • Organization  2M words × 32 bits × 4 banks • Package: Bare chip • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Clock frequency: 111MHz (max.)


    Original     		PDF ECS2532EECN-A 111MHz cycles/64ms M01E0107 E0697E50

    LBS11101

    Abstract: No abstract text available
    Text: 111MHz SAW Filter 3MHz Bandwidth China Electronics Technology Group Corporation No.26 Research Institute SIPAT Co., Ltd. Part Number:LBS11101 www.sipatsaw.com Specifications Parameter Unit Minimum Typical Maximum Center Frequency MHz 111.2 111.3 111.4 Insertion Loss


    Original     		PDF 111MHz LBS11101 LBS11101

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET 128M bits SDRAM Bare Chip ECS1232ECCN-A 4M words x 32 bits Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: Bare chip • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Clock frequency: 111MHz (max.)


    Original     		PDF ECS1232ECCN-A 111MHz cycles/64ms M01E0107 E0780E20

    Untitled

    Abstract: No abstract text available
    Text: K4M28163PF - R B G/F Mobile-SDRAM 2M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M28163PF is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the


    Original     		PDF K4M28163PF 16Bit 54CSP

    Untitled

    Abstract: No abstract text available
    Text: K4M64163PH - R B G/F Mobile-SDRAM 1M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M64163PH is 67,108,864 bits synchronous high data • LVCMOS compatible with multiplexed address. rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,


    Original     		PDF K4M64163PH 16Bit 54CSP

    K4M56163PG

    Abstract: 54-FBGA
    Text: K4M56163PG - R B E/G/C/F Mobile SDRAM 4M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M56163PG is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the


    Original     		PDF K4M56163PG 16Bit 54FBGA 54-FBGA

    K4M283233H

    Abstract: No abstract text available
    Text: K4M283233H - F H N/G/L/F Mobile SDRAM 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4M283233H is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,


    Original     		PDF K4M283233H 32Bit 90FBGA

    Untitled

    Abstract: No abstract text available
    Text: mult_vgen_v1.0.fm Page 1 Wednesday, October 13, 1999 9:03 AM Variable Parallel Virtex Multiplier V1.0.2 October 15, 1999 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com


    Original     		PDF

    LF9502

    Abstract: LMU217 ACCM 5 pin digital video mixer - tbc power supply 5 Volt LF3347 9027 scl110 LF3310 LF3311
    Text: Company Profile LOGIC Devices Incorporated develops and markets high-performance integrated circuits that are utilized in a wide range of video and medical imaging processing, telecommunications, computing and military smart weapon applications. LOGIC Devices is commited to providing its customers with the highest performing


    Original     		PDF 2002Short LF3310 LF3311 LF9502 LMU217 ACCM 5 pin digital video mixer - tbc power supply 5 Volt LF3347 9027 scl110 LF3310 LF3311

    PLSI 1016-60LJ

    Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
    Text: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density


    Original     		PDF 1016E 1032E 20ters 48-Pin 304-Pin PLSI 1016-60LJ PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT

    24-Pin Plastic DIP

    Abstract: e2cmos technology pioneer corporation
    Text: Introduction to ispGDXV , ispGDX and ispGDS Families TM TM TM Introduction Lattice Semiconductor Corporation, the pioneer of nonvolatile E2CMOS in-system programmable ISP logic, has now expanded the application of ISP PLDs to include programmable switching, interconnect and jumper functions with the ispGDX and the ispGDS devices. In-system


    Original     		PDF 111MHz 100-Pin 160-Pin 176-Pin 208-Pin 272-Ball 208-Ball 388-Pin ispGDX80A ispGDX80V 24-Pin Plastic DIP e2cmos technology pioneer corporation

    22V10 PAL CMOS device

    Abstract: Pal programming 22v10 29MA16 Vantis GAL16V8 16v8d 22v10 pal 20LV8D 16v8 PLD 74xx244 20V8
    Text: Introduction to GAL and PAL Devices ® output drive GAL16VP8 and GAL20VP8 , “zero power” operation (GAL16V8Z/ZD and GAL20V8Z/ZD), and insystem programmability (ispGAL22V10). Overview Lattice/Vantis, the inventor of the Generic Array Logic (GAL®) and Programmable Array Logic™ (PAL®) families of low density, E2CMOS® PLDs is the leading supplier


    Original     		PDF GAL16VP8 GAL20VP8) GAL16V8Z/ZD GAL20V8Z/ZD) ispGAL22V10) GAL22V10, PALCE22V10Q PALCE22V10Z ispGAL22V10 PALCE24V10 22V10 PAL CMOS device Pal programming 22v10 29MA16 Vantis GAL16V8 16v8d 22v10 pal 20LV8D 16v8 PLD 74xx244 20V8

    M12S16161A

    Abstract: M12S16161A-7BG M12S16161A-7TG
    Text: ESMT M12S16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z GENERAL DESCRIPTION JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 2 & 3


    Original     		PDF M12S16161A 16Bit M12S16161A M12S16161A-7BG M12S16161A-7TG

    K4M56323

    Abstract: K4M56323PG-F
    Text: K4M56323PG-F H E/G/C/F Mobile-SDRAM 2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M56323PG is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the


    Original     		PDF K4M56323PG-F 32Bit 90FBGA K4M56323PG K4M56323

    EDS2532EEBH-9A

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET 256M bits SDRAM EDS2532EEBH-9A 8M words x 32 bits Description Pin Configurations The EDS2532EEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the


    Original     		PDF EDS2532EEBH-9A EDS2532EEBH 90-ball 111MHz M01E0107 E0617E40 EDS2532EEBH-9A

    k4m641633

    Abstract: K4M641633K 54balls
    Text: K4M641633K - R B N/G/L/F Mobile-SDRAM 1M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4M641633K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,


    Original     		PDF K4M641633K 16Bit 54FBGA k4m641633 54balls

    adv7499

    Abstract: adv7402a LT 525I ADV7402 ADV7403 l e d colour tv circuit diagram P2401 av btr hex map 2N101 720P
    Text: a ADV7403 Integrated Multi-Format SDTV/HDTV Video Decoder and RGB Graphics Digitizer DATASHEET MANUAL January 2007 Confidential NDA Required ADV7403 1 INTRODUCTION . 1


    Original     		PDF ADV7403 adv7499 adv7402a LT 525I ADV7402 ADV7403 l e d colour tv circuit diagram P2401 av btr hex map 2N101 720P

    Untitled

    Abstract: No abstract text available
    Text: N128R3225GAK2 1M x 32Bit x 4Banks Double Data Rate Synchronous DRAM DISCRIPTION The N128R3225GAK2 is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400M bps/pin. I/O transactions are possible on both


    Original     		PDF N128R3225GAK2 32Bit N128R3225GAK2

    pioneer corporation

    Abstract: No abstract text available
    Text: Introduction to ispGDXV, ispGDX and ispGDS Families ® ® November 2003 Introduction Lattice Semiconductor Corporation, the pioneer of non-volatile E2CMOS® in-system programmable ISP logic, has now expanded the application of ISP PLDs to include programmable switching, interconnect and jumper functions with the ispGDX and the ispGDS devices. In-system programmability allows for real-time programming, less


    Original     		PDF 16-bit 100-Pin 160-Pin 176-Pin 208-Pin 208-Ball 272-Ball 388-Pin ispGDX80A ispGDX80VA pioneer corporation

    LF3320

    Abstract: LF3321
    Text: LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance FEATURES Selectable 16-bit Data Output with UserDefined Rounding and Limiting Supports Interleaved Data Streams Supports Decimation up to 16:1 for Increasing Number of Filter Taps


    Original     		PDF LF3321 16-bit 12-bit 24-bit) 32-Tap 12-bit, CFA11 CFA10 ROUT11 ROUT10 LF3320 LF3321

    LF3311

    Abstract: 743H LF3310 LF3320 RV15 VCF5 VCF9
    Text: LF3311 Horizontal / Vertical Digital Image Filter DEVICES INCORPORATED Improved Performance FEATURES 8 Vertical Filter Taps Two Operating Modes: Dimensionally Separate and Orthogonal Supports Interleaved Data Streams Horizontal Filter Supports Decimation up to


    Original     		PDF LF3311 12-bit 12-bit, DIN11 DIN10 HCF11 HCF10 311-A LF3311 743H LF3310 LF3320 RV15 VCF5 VCF9

    oneDRAM

    Abstract: 133MHz 640M 111MHz KJXX
    Text: One-DRAMTM Code Information 1/2 Last Updated : August 2009 KJXXXXXXXX - XXXXXXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 12. Package (AG01000 PKG SPEC Reference) A : FBGA (Lead-Free, Halogen-Free) S : FBGA (Lead-Free) 1. Memory (K) 2. OneDRAMTM : J 13. Temp, Power


    Original     		PDF AG01000 8K/64ms x16/x16 x32/x16 x16/x32 x32/x32 100MHz/100 oneDRAM 133MHz 640M 111MHz KJXX

    xilinx TURBO decoder

    Abstract: DS275 Turbo Code LogiCORE IP License Terms XC2V500 XC2VP20 Turbo decoder Xilinx RSC11
    Text: 3GPP2 Turbo Decoder v1.0 DS275 April 28, 2005 Product Specification Features Applications • Drop-in module for Spartan -3, Spartan-3E, This version of the TCC Turbo Convolution Code decoder is designed to meet the 3GPP2 mobile communication system specification [1].


    Original     		PDF DS275 CDMA2000/3GPP2 xilinx TURBO decoder Turbo Code LogiCORE IP License Terms XC2V500 XC2VP20 Turbo decoder Xilinx RSC11

    Untitled

    Abstract: No abstract text available
    Text: ADVANCED INFORMATION P L D 2 2 V 1 0 -7 High Performance 10-Macrocell CMOS PLD • High Speed Upgrade to BiCMOS/Bipolar 22V 10 and CMOS Equivalents ■ Global Asynchronous Clear and Synchronous Preset P-terms. ■ tpp 7.5ns, 111MHz with Feedback ■ 1-Micron CHMOS EPROM Technology


    OCR Scan     		PDF 10-Macrocell 111MHz 15MHz