119LEAD Search Results

119LEAD Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
GVT71256T18 Abstract: DQ974 Text: ADVANCE INFORMATION GALVANTECH, INC. SYNCHRONOUS CACHE TAG SRAM PIPELINED OUTPUT GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM 256K x 18 SRAM +3.3V SUPPLY WITH CLOCKED REGISTERED INPUTS FEATURES GENERAL DESCRIPTION • • • • • • The Galvantech Synchronous Burst SRAM family	Original	GVT71256T18 71256T18 access/10ns GVT71256T18 DQ974	PDF
71V2578 Abstract: No abstract text available Text: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA Description 128K x 36, 256K x 18 memory configurations	Original	IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA 150MHz 133MHz 100-pin x4033 71V2578	PDF
CY7C1386C Abstract: CY7C1387C Text: CY7C1386C CY7C1387C 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation	Original	CY7C1386C CY7C1387C 18-Mb 36/1M 250-MHz CY7C1386C/CY7C1387C CY7C1386C CY7C1387C	PDF
CY7C1360C-250BGC Abstract: CY7C1360C CY7C1362C CY7C1360C-166BZI Text: CY7C1360C CY7C1362C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz	Original	CY7C1360C CY7C1362C 36/512K 250-MHz 200-MHz 166-MHz CY7C1360C-250BGC CY7C1360C CY7C1362C CY7C1360C-166BZI	PDF
CY7C1325G Abstract: CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI Text: CY7C1325G PRELIMINARY 4-Mbit 256K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 256K X 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)	Original	CY7C1325G 133-MHz 117-MHz 100-MHz 100-pin 119-ball CY7C1325G CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI	PDF
CY7C1327B Abstract: No abstract text available Text: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states	Original	CY7C1327B CY7C1327B 100-MHz 166-MHz 166-Mpress	PDF
CY7C1381B-100AI Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B Text: 381B CY7C1381B CY7C1383B 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion	Original	CY7C1381B CY7C1383B 36/1M CY7C1381B/CY7C1383B x36/1M CY7C1381B-100AI 381B CY7C1381B CY7C1381B-117AC CY7C1383B	PDF
80486 microprocessor block diagram and pin diagram Abstract: CY7C1338B Text: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence	Original	CY7C1338B 117-MHz 100-pin CY7C1338B 80486 microprocessor block diagram and pin diagram	PDF
CY7C1327G Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI Text: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times	Original	CY7C1327G 250-MHz 225-MHz 200-MHz CY7C1327G CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI	PDF
GVT71256ZC36B-7.5 Abstract: CY7C1356A-100AC CY7C1356A GVT71512ZC18 Text: PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 133, and 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns	Original	CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 GVT71256ZC36B-7.5 CY7C1356A-100AC CY7C1356A GVT71512ZC18	PDF
CY7C1381A Abstract: CY7C1381A-100AC CY7C1381A-117AC CY7C1381A-83AC Text: CY7C1381A CY7C1383A PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 9.0, 10.0 ns Fast clock speed: 117, 100, 83, 66 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion	Original	CY7C1381A CY7C1383A CY7C1381A CY7C1381A-100AC CY7C1381A-117AC CY7C1381A-83AC	PDF
CY7C1357A Abstract: GVT71512ZB18 Text: 1CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns	Original	1CY7C1357A CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 CY7C1357A GVT71512ZB18	PDF
CY7C1380BV25 Abstract: CY7C1382BV25 Text: 1CY7C1380BV25 CY7C1380BV25 CY7C1382BV25 PRELIMINARY 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns	Original	1CY7C1380BV25 CY7C1380BV25 CY7C1382BV25 CY7C1380BV25 CY7C1382BV25	PDF
Untitled Abstract: No abstract text available Text: CY7C1361C CY7C1363C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed	Original	CY7C1361C CY7C1363C 36/512K 133-MHz CY7C1361C/CY7C1363C	PDF

CY7C1338B Abstract: 80486 microprocessor block diagram and pin diagrams Text: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence	Original	CY7C1338B 117-MHz 100-pin CY7C1338B BG119) 80486 microprocessor block diagram and pin diagrams	PDF
CY7C1444V33 Abstract: CY7C1444V33-300AC CY7C1444V33-300BGC CY7C1444V33-300BZC CY7C1445V33 CY7C1445V33-300AC CY7C1445V33-300BGC Text: CY7C1445V33 CY7C1444V33 PRELIMINARY 1M x 36/2M x 18 Pipelined DCD SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.3, 2.7, 3.0, and 3.5 ns	Original	CY7C1445V33 CY7C1444V33 36/2M CY7C1444V33/CY7C1445V33 CY7C1444V33 CY7C1444V33-300AC CY7C1444V33-300BGC CY7C1444V33-300BZC CY7C1445V33 CY7C1445V33-300AC CY7C1445V33-300BGC	PDF
CY7C1347B Abstract: memory depth expansion Text: 1CY7C1347 CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium  and PowerPC operations with zero wait states	Original	1CY7C1347 CY7C1347B CY7C1347B 100-MHz 166-MHz memory depth expansion	PDF
CY7C1347D Abstract: CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC Text: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time	Original	CY7C1347D CY7C1347D: CY7C1347D CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC	PDF
CY7C1372A Abstract: No abstract text available Text: CY7C1370A CY7C1372A PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 167, 150, 133, and 100 MHz • Fast access time: 3.4, 3.8, 4.2, 5.0 ns	Original	CY7C1370A CY7C1372A 512Kx36/1Mx18 CY7C1372A	PDF
Untitled Abstract: No abstract text available Text: 128K X 36, 256K X 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, FLOW-THROUGH OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT i :$&& 4« »»« tK fc « 'S * * * * ; 4ÎK «« ^ iL j; PRELIMINARY IDT71V2577 IDT71V2579 IDT71V3577 IDT71V3579 FE A TU R E S :	OCR Scan	IDT71V2577 IDT71V2579 IDT71V3577 IDT71V3579 IDT71 Vx577/579 -544-SRAM	PDF
Untitled Abstract: No abstract text available Text: 128K X 36, 256K X 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, PIPELINED OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT D E S C R IP T IO N : FE A TU R E S : • 128K x 36,256K x 18 memory configurations • Supports high system speed: - PRELIMINARY IDT71V2576	OCR Scan	IDT71V2576 IDT71V2578 IDT71V3576 IDT71V3578 IDT71 Vx576/578 83MHz 66MHz	PDF
Untitled Abstract: No abstract text available Text: Æ SW ««K B » 128K X 36, 256K X 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, FLOW-THROUGH OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT D E S C R IP T IO N : The IDT71Vx577/579 are high-speed SRAMs organized as 128K x 36/ 256K x 18. The IDT71Vx577/579 SRAMs contain write, data, address	OCR Scan	IDT71Vx577/579 IDT71 Vx577/579 -544-SRAM	PDF
Untitled Abstract: No abstract text available Text: i 128K X 36, 256KX 18, 3.3V SYNCHRONOUS SRAMS WITH ZBT FEATURE, BURST COUNTER AND FLOW-THROUGH OUTPUTS :$&& 4« »»« tK fc « 'S * * * * ; 4ÎK«« '* * * « ^ iL j; PRELIMINARY IDT71 V2557,IDT71 V2559 IDT71V3557, IDT71V3559 FEATURES: The IDT71 Vx557/59 contain address, data-in and control signal regis	OCR Scan	256KX IDT71 V2557 V2559 IDT71V3557, IDT71V3559 Vx557/59	PDF
Untitled Abstract: No abstract text available Text: 1 2 8 K X 3 6 ,2 5 6 K X 1 8 ,3.3V SYNCHRONOUS SRAMS WITH PRELIMINARY 3.3V I/O, FLOW-THROUGH OUTPUTS, IDT71V3577 BURSTCOUNTER, IDT71V3579 SINGLE CYCLE DESELECT D e sc rip tio n F ea tu re s The IDT71V3577/79 are high-speed SRAMs organized as * 128K x 3 6 ,256K x 18 memory configurations	OCR Scan	IDT71V3577 IDT71V3579 IDT71V3577/79 36/256K 100-lead 119-lead 71V3577 71V3579	PDF

119LEAD Search Results

119LEAD Datasheets Context Search

GVT71256T18

71V2578

CY7C1386C

CY7C1360C-250BGC

CY7C1325G

CY7C1327B

CY7C1381B-100AI

80486 microprocessor block diagram and pin diagram

CY7C1327G

GVT71256ZC36B-7.5

CY7C1381A

CY7C1357A

CY7C1380BV25

Untitled

CY7C1338B

CY7C1444V33

CY7C1347B

CY7C1347D

CY7C1372A

Untitled

Untitled

Untitled

Untitled

Untitled