TGA4817-EPU
Abstract: No abstract text available
Text: Advance Product Information December 18, 2003 10Gb/s Wide Dynamic Range Differential TIA TGA4817-EPU Key Features and Performance • • • • • • • • 3200Ω Single-Ended Transimpedance > 9 GHz 3dB Bandwidth > 1.6mA RMS Input Overload Current 11pA/ √Hz Input Noise Current
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10Gb/s
TGA4817-EPU
0007-inch
TGA4817-EPU
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MT29F2G08AAC
Abstract: SD-Card MMC AT91 5V ATMEL AT91 serial isp atmel AT91SAM-ICE
Text: ARM-Based Products Application Group AT91SAM9RL-EK Test Software Revision Table: Revision 3.0 3.1 Date June 13, 2008 August 19,2008 Comments Initial release 1.update AT91 ISP and Jlink driver 2.add LCD demo 1/11pages ARM-Based Products Application Group Table of Contents
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AT91SAM9RL-EK
1/11pages
AT91xxxxx
10/11pages
AT91SAM9RL64EK
AT91SAM9RL-EK.
11/11pages
MT29F2G08AAC
SD-Card MMC
AT91 5V
ATMEL AT91
serial isp atmel
AT91SAM-ICE
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ADN29
Abstract: No abstract text available
Text: PRELIMINARY TECHNICAL DATA a 10.7 Gbps 3.3V LOW NOISE HIGH GAIN TIA WITH PERFORMANCE MONITORS Preliminary Technical Data ADN2820 FEATURES Technology: High Performance SiGe Bandwidth: 9GHz Input Noise Current Density: 11pA/ root Hz Optical sensitivity: -19.3 dBm1
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ADN2820
250mW
100mV
OC-192/STM-64
ADN282rrent
05Sept02
DN2820
870mm
060mm
ADN29
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Untitled
Abstract: No abstract text available
Text: Datasheet for part number CA3100E28-11PA176 Our Catalog Part Number: CA3100E28-11P-A176 Brand: Cannon Product Category: Circular Product Line: MIL-DTL 5015 Series I Series: MIL-C-5015 Product Datasheet Thread Shell Style Endbell Style Gender Shell Size Contact Arrangement
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CA3100E28-11PA176
CA3100E28-11P-A176
MIL-C-5015
15/15S/16/16S)
15/uminium
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E112081
Abstract: No abstract text available
Text: FicheE7/ASDrightangle22/05/0118:11Page2 SD D'Sub connectors - Stamped and Formed Contacts Spécifications DESCRIPTION MAIN CHARACTERISTICS RIGHT ANGLE, BOARD MOUNT CONNECTORS • A4 Style MIL footprint : UL File: E149426 • 1A Style (European footprint): UL File: E112081
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E149426
E112081
C24308
93425-HE5
E112081
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OC74
Abstract: No abstract text available
Text: Advance Product Information September 27, 2004 10Gb/s Wide Dynamic Range Differential TIA TGA4817-EPU Key Features and Performance • • • • • • • • Preliminary Measured Performance Bias Conditions: V+=3.3V I+=70mA 76 Differential Zt dB-Ohm
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10Gb/s
TGA4817-EPU
0007-inch
OC74
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KH103
Abstract: KH300 KH300A LF356A
Text: www.fairchildsemi.com KH300 Wideband, High-Speed Operational Amplifier Features • ■ ■ ■ ■ General Description -3dB bandwidth of 85MHz 3000V/µsec slew rate 4ns rise and fall time 100mA output current Low distortion, linear phase Applications ■
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KH300
85MHz
100mA
KH300
KH103
KH300A
LF356A
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Untitled
Abstract: No abstract text available
Text: 56F8037/56F8027 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8037 Rev. 8 04/2012 freescale.com Document Revision History Version History Description of Change Rev. 0 Initial public release. Rev. 1 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase
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56F8037/56F8027
56F8000
16-bit
MC56F8037
400kHz
200kHz.
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pso88
Abstract: No abstract text available
Text: OPA2607 OPA 260 7 OPA 260 7 For most current data sheet and other product information, visit www.burr-brown.com Dual, High Output, Current-Feedback OPERATIONAL AMPLIFIER TM FEATURES DESCRIPTION ● WIDEBAND ±12V OPERATION: 25MHz G = +8 ● UNITY GAIN STABLE: 35MHz (G = +1)
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OPA2607
25MHz
35MHz
250mA
SO-14)
OPA2607
pso88
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sim 900A
Abstract: No abstract text available
Text: 56F8355/56F8155 Data Sheet Preliminary Technical Data 56F8300 16-Bit Digital Signal Controllers MC56F8355 Rev. 14 06/2009 freescale.com Document Revision History Version History Description of Change Rev 0.0 Initial release Rev 1.0 Fixed typos in Section 1.1.3; Replace any reference to Flash Interface Unit with Flash
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56F8355/56F8155
56F8300
16-Bit
MC56F8355
sim 900A
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PAP-07V-S
Abstract: S03B-PASK-2 PARP-08V SPAL001-05 BM08B-PASS SM02B-PASS SPAL002TP0
Text: PA FAMILY SERIES/PA•PAF•PAL CONNECTOR Wire-to-board Crimp style/IDC / Wire-to-wire (Crimp style/IDC) 2.0mm (.079") pitch Features –––––––––––––––––––––––– • Secure locking device The housing has a locking device to prevent accidental
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type/250V
type/100V
PAP-07V-S
S03B-PASK-2
PARP-08V
SPAL001-05
BM08B-PASS
SM02B-PASS
SPAL002TP0
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crimp jst Spa-001t-p0.5
Abstract: BM06B-PASS SM02B-PASS BH04B-PASK-1 sm03b-pass SM10B-PASS-1 BM04B-PASS BH02B-PASK-1 BM10B-PASS BM08B-PASS
Text: PA ラジアル FAMILY SERIES/PA•PAF•PAL CONNECTOR 2.0mm pitch/Wire-to-board Crimp style/IDC / Wire-to-wire (Crimp style/IDC) Standards –––––––––––––––––––––– Retainer PA Receptacle (Crimp style Standard type)
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CLC5623
Abstract: CLC5623IM CLC5623IMX CLC5623IN M14A N14A SPICE2G6 4501m
Text: ご注意：この日本語データシートは参考資料として提供しており内容 が最新でない場合があります。製品のご検討およびご採用に際 しては、必ず最新の英文データシートをご確認ください。
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CLC5623
130mA)
15MHz
148MHz
nat2000
ds015004
96dBc
1000pF
CLC5623
CLC5623IM
CLC5623IMX
CLC5623IN
M14A
N14A
SPICE2G6
4501m
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LF356A
Abstract: KH103 KH300 KH300A d 1275
Text: www.cadeka.com KH300 Wideband, High-Speed Operational Amplifier Features • ■ ■ ■ ■ General Description -3dB bandwidth of 85MHz 3000V/µsec slew rate 4ns rise and fall time 100mA output current Low distortion, linear phase Applications ■ ■ ■
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KH300
85MHz
100mA
KH300
LF356A
KH103
KH300A
d 1275
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Untitled
Abstract: No abstract text available
Text: M AX 9000 Programmable Logic Device Family June 1996, VBr. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ H igh-perform ance CM OS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array M atrix
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12-ns
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SCAS142A-D3791
Abstract: TTL Schmitt-Trigger Inverters six independent Schmitt-trigger inverters 74ACT11014
Text: 74ACT11014 HEX SCHMITT-TRIGGER INVERTER SC A S 142A -03791. FEBRUARY 1991 -R E V IS E D APRIL1993 DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise
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74ACT11014
APRIL1993
500-mA
300-mll
AS142A-D3791,
SCAS142A-D3791
TTL Schmitt-Trigger Inverters
six independent Schmitt-trigger inverters
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Untitled
Abstract: No abstract text available
Text: SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS _ SCAS303F - JANUARY 1993 - REVISED JANUARY 1998 EPIC Enhanced-Performartce Implanted CMOS Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C
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SN54LVC652A,
SN74LVC652A
SCAS303F
MIL-STD-833,
SN74LVC652A.
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ST 9241
Abstract: No abstract text available
Text: DW9241 M ITEL 78.81MHz Low Loss SAW IF Filter S E M IC O N D U C T O R D S 3 5 3 2 - 1.4 O c to b e r 1995 T he DW 9241 has been sp e cifica lly d e velope d for the P e rs o n a l C o m m u n ic a tio n s m a rke t, w h e re th e 1st I.F. sta g e filte r is typ ica lly in the 60 to 80 M H z range.
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DW9241
81MHz
ST 9241
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Untitled
Abstract: No abstract text available
Text: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM H IT A C H I ADE-203-280B Z Rev. 2.0 Jun. 20, 1997 Description All inputs and outputs are referred to the lising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.
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HM5216165
288-word
16-bit
ADE-203-280B
Hz/83
HM5216165-10H
HM5216165-10H)
HM5216165-10/15
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Untitled
Abstract: No abstract text available
Text: HM5264165 Series HM5264805 Series HM5264405 Series 1,048,576-word X 16-bit x 4-bank Synchronous Dynamic RAM 2,097,152-word X 8-bit x 4-bank Synchronous Dynamic RAM 4,194,304-word X 4-bit X 4-bank Synchronous Dynamic RAM HITACHI ADE-203-497 Z Preliminary Rev. 0.3
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HM5264165
HM5264805
HM5264405
576-word
16-bit
152-word
304-word
ADE-203-497
HM5264165,
HM5264805,
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Untitled
Abstract: No abstract text available
Text: Features * Single 2.7V - 3.6V Supply * Serial Interface Architecture * Page Program Operation - Single Cycle Reprogram Erase and Program - 4096 Pages (264 Bytes/Page) Main Memory * Two 264-byte SRAM Data Buffers - Allows Receiving of Data while Reprogramming of
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264-byte
0870C
04/99/xM
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Untitled
Abstract: No abstract text available
Text: Features * Single 4.5V - 5.5V Supply * Serial Interface Architecture * Page Program Operation - Single Cycle Reprogram Erase and Program - 4096 Pages (528 Bytes/Page) Main Memory * Optional Page and Block Erase Operations * Two 528-Byte SRAM Data Buffers - Allows Receiving of Data while Reprogramming of
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528-Byte
06/98/XM
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Untitled
Abstract: No abstract text available
Text: Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation -S in g le Cycle Reprogram Erase and Program - 4096 Pages (264 Bytes/Page) Main Memory • Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of
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264-Byte
AT45D081
AT45D081-RI
AT45D081-TI
28-Lead,
32-Lead,
AT45D081
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET_ BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT uPB1005GS REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz RF/IF FREQUENCY DOWNCONVERTER + PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER DESCRIPTION The ^¡PB1005GS is a silicon monolithic integrated circuit for GPS receiver.
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uPB1005GS
PB1005GS
30-pin
PB100e:
WS60-00-1
C10535E)
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