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    128KX36 Search Results

    128KX36 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    71V2546S133BGI8 Renesas Electronics Corporation 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O Visit Renesas Electronics Corporation
    71V2556S100PFGI8 Renesas Electronics Corporation 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O Visit Renesas Electronics Corporation
    71V2556S166PFG8 Renesas Electronics Corporation 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O Visit Renesas Electronics Corporation
    71V2556SA100BGI8 Renesas Electronics Corporation 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O Visit Renesas Electronics Corporation
    71V3556S166PFG Renesas Electronics Corporation 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 3.3V I/O Visit Renesas Electronics Corporation

    128KX36 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    IBM0418A41NLAB

    Abstract: IBM0418A81NLAB IBM0436A41NLAB IBM0436A81NLAB
    Text: IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM . Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • Registered outputs • 30 Ω drivers


    Original     		IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crrL3325 IBM0418A41NLAB IBM0436A81NLAB PDF

    K7A401800B-QC

    Abstract: K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC
    Text: K7A403609B K7A403209B K7A401809B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters


    Original     		K7A403609B K7A403209B K7A401809B 128Kx36/x32 256Kx18 128Kx36 128Kx32 256Kx18-Bit 570mA 490mA K7A401800B-QC K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC PDF

    K7A401800B

    Abstract: K7A401800B-QC K7A401809B-QC K7A403200B K7A403200B-QC K7A403209B-QC K7A403600B K7B401825B-QC K7B403225B-QC
    Text: K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters


    Original     		K7A403600B K7A403200B K7A401800B 128Kx36/x32 256Kx18 128Kx36 128Kx32 256Kx18-Bit 350mA 290mA K7A401800B K7A401800B-QC K7A401809B-QC K7A403200B K7A403200B-QC K7A403209B-QC K7A403600B K7B401825B-QC K7B403225B-QC PDF

    IBM0418A8ACLAB

    Abstract: IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB
    Text: . IBM0418A4ACLAB IBM0436A8ACLAB Preliminary IBM0418A8ACLAB IBM0436A4ACLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology


    Original     		IBM0418A4ACLAB IBM0436A8ACLAB IBM0418A8ACLAB IBM0436A4ACLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crlh3320 IBM0418A8ACLAB IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB PDF

    K7N401801B

    Abstract: K7N403601B
    Text: K7N403601B K7N401801B 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 350mA to 290mA at -16,


    Original     		K7N403601B K7N401801B 128Kx36 256Kx18 256Kx18-Bit 350mA 290mA 330mA 270mA K7N401801B K7N403601B PDF

    CY7C1350

    Abstract: IDT71V546 MCM63Z736
    Text: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait


    Original     		CY7C1350 128Kx36 IDT71V546, MT55L128L36P MCM63Z736 143-MHz CY7C1350 IDT71V546 MCM63Z736 PDF

    IBM0418A4ANLAB

    Abstract: IBM0418A8ANLAB IBM0436A4ANLAB IBM0436A8ANLAB
    Text: . Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25µ CMOS technology • Synchronous Register-Latch Mode of Operation


    Original     		IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crlL3325 IBM0418A8ANLAB IBM0436A4ANLAB PDF

    IBM0418A41XLAB

    Abstract: IBM0418A81XLAB IBM0436A41XLAB IBM0436A81XLAB
    Text: . Preliminary IBM0418A81XLAB IBM0436A81XLAB IBM0418A41XLAB IBM0436A41XLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology


    Original     		IBM0418A81XLAB IBM0436A81XLAB IBM0418A41XLAB IBM0436A41XLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crrh2516 IBM0418A41XLAB IBM0418A81XLAB IBM0436A41XLAB IBM0436A81XLAB PDF

    7C1351-40

    Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737
    Text: fax id: 1102 CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states


    Original     		CY7C1351 128Kx36 IDT71V547, MT55L128L36F MCM63Z737 66-MHz CY7C1351 7C1351-40 7C1351-50 7C1351-66 IDT71V547 MCM63Z737 PDF

    Untitled

    Abstract: No abstract text available
    Text: K7N403609B K7N403209B K7N401809B 128Kx36/x32 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters


    Original     		K7N403609B K7N403209B K7N401809B 128Kx36/x32 256Kx18 128Kx36 128Kx32 256Kx18-Bit 470mA 400mA PDF

    Untitled

    Abstract: No abstract text available
    Text: K7P403611M K7P401811M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.


    Original     		K7P403611M K7P401811M 128Kx36 256Kx18 PDF

    Untitled

    Abstract: No abstract text available
    Text: K7B403625B K7B403225B K7B401825B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters


    Original     		K7B403625B K7B403225B K7B401825B 128Kx36/x32 256Kx18 128Kx36 128Kx32 256Kx18-Bit 300mA 250mA PDF

    Untitled

    Abstract: No abstract text available
    Text: K7P403623M K7P401823M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.


    Original     		K7P403623M K7P401823M 128Kx36 256Kx18 119BGA PDF

    KM718FV4011H-5

    Abstract: KM718FV4011H-6 KM736FV4011H-5 KM736FV4011H-6 SA10 SA12 SA13 SA15
    Text: KM736FV4011 KM718FV4011 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.


    Original     		KM736FV4011 KM718FV4011 128Kx36 256Kx18 KM718FV4011H-5 KM718FV4011H-6 KM736FV4011H-5 KM736FV4011H-6 SA10 SA12 SA13 SA15 PDF

    SA15

    Abstract: K7P401811M K7P403611M SA10 SA12 SA13
    Text: K7P403611M K7P401811M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.


    Original     		K7P403611M K7P401811M 128Kx36 256Kx18 SA15 K7P401811M K7P403611M SA10 SA12 SA13 PDF

    7C1351-40

    Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737 DQ31-0
    Text: fax id: 1102 Back CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states


    Original     		CY7C1351 128Kx36 IDT71V547, MT55L128L36F MCM63Z737 66-MHz CY7C1351 7C1351-40 7C1351-50 7C1351-66 IDT71V547 MCM63Z737 DQ31-0 PDF

    K7N401801M

    Abstract: K7N403601M
    Text: K7N403601M K7N401801M 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAM TM Revision History History Draft Date Remark 0.0 1. Initial document. July.06. 1998 Preliminary 0.1 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75


    Original     		K7N403601M K7N401801M 128Kx36 256Kx18 256Kx18-Bit K7N401801M K7N403601M PDF

    Untitled

    Abstract: No abstract text available
    Text: I = = = = •= Preliminary IBM0418A81QLAA IBM0418A41 QLAA IBM0436A81QLAA IBM0436A41QLAA 8Mb 256Kx36 & 512x18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 256K x 36 or 512K x 18 organizations • Registered Outputs • 128K x 36 or 256K x 18 organizations


    OCR Scan     		IBM0418A81QLAA IBM0418A41 IBM0436A81QLAA IBM0436A41QLAA 256Kx36 512x18) 128Kx36 256Kx18) PDF

    Untitled

    Abstract: No abstract text available
    Text: I = =• = Preliminary IBM0418A80QLAB IBM0418A40QLAB IBM0436A80QLAB IBM0436A40QLAB 8Mb 256Kx36 & 512x18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 256K x 36 or 512K x 18 Organizations • Registered Addresses, W rite Enables, Synchro­ nous Select, and Data Ins.


    OCR Scan     		IBM0418A80QLAB IBM0418A40QLAB IBM0436A80QLAB IBM0436A40QLAB 256Kx36 512x18) 128Kx36 256Kx18) PDF

    CY7C1350

    Abstract: No abstract text available
    Text: fax id: 1103 * g S S M ^ % rrv rt n n n CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture F e a tu re s F u n c t io n a l D e s c r ip t io n • Pin compatible and functionally e q u iv a le n ts ZBT™ devices IDT71V546, MT55L128L36P and MCM63Z736


    OCR Scan     		CY7C1350 128Kx36 IDT71V546, MT55L128L36P MCM63Z736 CY7C1350 143-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: KM736V789 128Kx36 Synchronous SRAM D o c u m e n t T itle 128Kx36-Bit Synchronous Pipelined Burst SRAM R e v is iflü - H is io r y Rev. No. History Draft Date Remark 0.0 Initial draft May . 15. 1997 Preliminary 0.1 Change 7.5 bin to 7.2 January . 13 . 1998


    OCR Scan     		KM736V789 128Kx36 128Kx36-Bit 100-TQFP-1420A 50REF PDF

    Untitled

    Abstract: No abstract text available
    Text: KM736FV4022 KM718FV4022 PRELIMINARY 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.


    OCR Scan     		KM736FV4022 KM718FV4022 128Kx36 256Kx18 50REF PDF

    Untitled

    Abstract: No abstract text available
    Text: KM736V787 PRELIMINARY 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Burst SRAM Revision History Rev.No. History Draft Date 0.0 Initial draft May. 15. 1997 0.1 Modify power down cycle timing & Interleaved read timing, Feb. 11.19 9 8 Remark


    OCR Scan     		KM736V787 128Kx36 128Kx36-Bit 100-TQFP-1420A PDF

    EOIZ

    Abstract: No abstract text available
    Text: CY7C1351 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description The CY7C1351 is a 3.3V 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the


    OCR Scan     		CY7C1351 128Kx36 IDT71V547, MT55L128L36F, MCM63Z737 66-MHz EOIZ PDF