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1364V25 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
CY7C1360 Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82 Text: CY7C1360V25 CY7C1362V25 1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device	Original	PDF	CY7C1360V25 CY7C1362V25 CY7C1364V25 36/256K 32/512K 200-MHz 166-MHz 133-MHz 100-MHz CY7C1360 CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82
CY7C1360V25 Abstract: CY7C1362V25 CY7C1364V25 Text: 329 CY7C1360V25 CY7C1362V25 1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device	Original	PDF	CY7C1360V25 CY7C1362V25 CY7C1364V25 36/256K 32/512K 200-MHz 166-MHz 133-MHz 100-MHz CY7C1360V25 CY7C1362V25 CY7C1364V25
M-25012 states Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25 Text: ^ „ CY7C1360V25 CY7C1362V25 W ^ T Y P R F .S S PREUm NARY CY7C 1364V25 256K X 36/256K x 32/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max	OCR Scan	PDF	CY7C1360V25 CY7C1362V2 CY7C1364V25 36/256K 32/512K 200-MHz 166-MHz 133-MHz 100-MHz M-25012 states CY7C1360V25 CY7C1362V25 CY7C1364V25

Catalog Datasheet

MFG & Type

PDF

Document Tags

CY7C1360

Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82
Text: CY7C1360V25 CY7C1362V25 1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device

Original

PDF

CY7C1360V25 CY7C1362V25 CY7C1364V25 36/256K 32/512K 200-MHz 166-MHz 133-MHz 100-MHz CY7C1360 CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82

CY7C1360V25

Abstract: CY7C1362V25 CY7C1364V25
Text: 329 CY7C1360V25 CY7C1362V25 1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device

Original

PDF

CY7C1360V25 CY7C1362V25 CY7C1364V25 36/256K 32/512K 200-MHz 166-MHz 133-MHz 100-MHz CY7C1360V25 CY7C1362V25 CY7C1364V25

M-25012 states

Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25
Text: ^ „ CY7C1360V25 CY7C1362V25 W ^ T Y P R F .S S PREUm NARY CY7C 1364V25 256K X 36/256K x 32/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max

OCR Scan

PDF

CY7C1360V25 CY7C1362V2 CY7C1364V25 36/256K 32/512K 200-MHz 166-MHz 133-MHz 100-MHz M-25012 states CY7C1360V25 CY7C1362V25 CY7C1364V25