INA2128
Abstract: INA2128U INA2128UA SOIC-16
Text: INA2128 INA 212 8 INA 212 8 SBOS035A – DECEMBER 1995 – REVISED APRIL 2007 Dual, Low Power INSTRUMENTATION AMPLIFIER DESCRIPTION FEATURES ● ● ● ● ● ● ● ● LOW OFFSET VOLTAGE: 50µV max LOW DRIFT: 0.5µV/°C max LOW INPUT BIAS CURRENT: 5nA max
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INA2128
SBOS035A
120dB
16-PIN
SOL-16
INA2128
200kHz
INA2128U
INA2128UA
SOIC-16
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STM32F103xE
Abstract: LQPF100 FOOTPRINTS BGA64 LQFP100 LQFP48 LQFP64 STM32F103C8 STM32F103RB AN2606 STM32F103CBT6
Text: STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F103x8
STM32F103xB
32-bit
4-to-16
STM32F103xE
LQPF100 FOOTPRINTS
BGA64
LQFP100
LQFP48
LQFP64
STM32F103C8
STM32F103RB
AN2606
STM32F103CBT6
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STM32 LQFP-64 footprint
Abstract: rain alarm CIRCUIT using IC 555 vfQFPn-36 footprint LQFP100 LQFP48 LQFP64 STM32F101 QFN-36 STM32F10xxx jtag
Text: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1 performance at 0 wait state memory
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STM32F101x8
STM32F101xB
32-bit
4-to-16
STM32 LQFP-64 footprint
rain alarm CIRCUIT using IC 555
vfQFPn-36 footprint
LQFP100
LQFP48
LQFP64
STM32F101
QFN-36
STM32F10xxx jtag
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STM32F103Cx
Abstract: STM32F103Rx vfQFPn-36 footprint stm32f10x manual timer pwm STM32F10x STM32F103xB STM32F103Tx
Text: STM32F103x6 STM32F103x8 STM32F103xB Performance line, ARM-based 32-bit MCU with up to 128 KB Flash, USB, CAN, seven 16-bit timers, 2 ADCs & 9 communication interfaces Features • ■ ■ Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F103x6
STM32F103x8
STM32F103xB
32-bit
16-bit
4-to-16
STM32F103Cx
STM32F103Rx
vfQFPn-36 footprint
stm32f10x manual timer pwm
STM32F10x
STM32F103xB
STM32F103Tx
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LQFP100
Abstract: LQFP48 LQFP64
Text: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1 performance at 0 wait state memory
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STM32F101x8
STM32F101xB
32-bit
4-to-16
LQFP100
LQFP48
LQFP64
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Untitled
Abstract: No abstract text available
Text: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1 performance at 0 wait state memory
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STM32F101x8
STM32F101xB
32-bit
LQFP48
4-to-16
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6TPD330M
Abstract: C3225X5R1C106M SLMA002 TPS54010 TPS54010PWP TPS54010PWPR
Text: Typical Size 6,4 mm X 9,7 mm TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 2.2 – 4 -V, 14-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs SWIFT FEATURES • • • • • • • • • DESCRIPTION Separate Low-Voltage Power Bus
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TPS54010
SLVS509B
6TPD330M
C3225X5R1C106M
SLMA002
TPS54010
TPS54010PWP
TPS54010PWPR
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Untitled
Abstract: No abstract text available
Text: SN74LV4053AĆQ1 TRIPLE 2ĆCHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS521A − AUGUST 2003 − REVISED MAY 2004 D Qualification in Accordance With D OR PW PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control
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SN74LV4053AQ1
SCLS521A
AEC-Q100
MIL-STD-883,
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Untitled
Abstract: No abstract text available
Text: SN74HCT04ĆQ1 HEX INVERTER SCLS535 − AUGUST 2003 D Qualification in Accordance With D D D D D D D AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per
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SN74HCT04Q1
SCLS535
AEC-Q100
MIL-STD-883,
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Untitled
Abstract: No abstract text available
Text: SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS SLLS459C − NOVEMBER 2000 − REVISED MARCH 2005 D Three Differential Transceivers in One D D D D D D D D D D D Package Signaling Rates† Up to 30 Mbps Low Power and High Speed Designed for TIA/EIA-485, TIA/EIA-422, ISO
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SN65LBC170,
SN75LBC170
SLLS459C
TIA/EIA-485,
TIA/EIA-422,
SN75ALS170
SN65LBC170DB
BL170)
SN75LBC170DB
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IXYS DSE160-06A
Abstract: DSE160-06A dse160-06
Text: DRV103 D RV DRV 103 103 SBVS029A – JUNE 2001 PWM LOW-SIDE DRIVER 1.5A and 3A for Solenoids, Coils, Valves, Heaters, and Lamps FEATURES DESCRIPTION ● HIGH OUTPUT DRIVE: 1.5A and 3A Versions ● WIDE SUPPLY RANGE: +8V to +32V ● COMPLETE FUNCTION Digitally Controlled Input
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DRV103
SBVS029A
500Hz
100kHz
DRV103
IXYS DSE160-06A
DSE160-06A
dse160-06
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PG715
Abstract: A115-A C101 P82B715 P82B715D P82B715P
Text: P82B715 I2C BUS EXTENDER www.ti.com SCPS145A – DECEMBER 2007 – REVISED FEBRUARY 2008 FEATURES 1 • • • • • Operating Power-Supply Voltage Range of 3 V to 12 V Supports Bidirectional Data Transfer of I2C Bus Signals Allows Bus Capacitance of 400 pF on Main I2C
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P82B715
SCPS145A
PG715
A115-A
C101
P82B715
P82B715D
P82B715P
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Untitled
Abstract: No abstract text available
Text: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F101x8
STM32F101xB
32-bit
LQFP48
4-to-16
DocID13586
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Untitled
Abstract: No abstract text available
Text: STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Datasheet − production data Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F101x8
STM32F101xB
32-bit
LQFP48
4-to-16
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PC13-TAMPERRTC
Abstract: No abstract text available
Text: STM32F101x6 STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 32 to 128 KB Flash, six timers, ADC and 7 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F101x6
STM32F101x8
STM32F101xB
32-bit
4-to-16
PC13-TAMPERRTC
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STMPE1601
Abstract: No abstract text available
Text: STMPE1601 16-bit enhanced port expander with keypad and PWM controller Xpander Logic Preliminary Data Features • 16 GPIOs 8 operate at core supply VCC , 8 operate at IO supply Vio ■ Operating voltage 1.8 − 3.3 V ■ Hardware keypad controller (8*8 matrix with 4
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STMPE1601
16-bit
TFBGA25
STMPE1601
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stm32f101xx PWM
Abstract: No abstract text available
Text: STM32F101x6 STM32F101x8 STM32F101xB Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F101x6
STM32F101x8
STM32F101xB
32-bit
16-bit
4-to-16
stm32f101xx PWM
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6TPD330M
Abstract: C3225X5R1C106M SLMA002 TPS54010 TPS54010PWP TPS54010PWPR
Text: Typical Size 6,4 mm X 9,7 mm TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 2.2 – 4 -V, 14-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs SWIFT FEATURES • • • • • • • • • DESCRIPTION Separate Low-Voltage Power Bus
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TPS54010
SLVS509B
6TPD330M
C3225X5R1C106M
SLMA002
TPS54010
TPS54010PWP
TPS54010PWPR
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stm32f103xx
Abstract: STM32F103Tx STM32 LQFP-64 footprint FT2384 LQFP100 LQFP48 LQFP64 STM32F103C6 STM32F103C8 STM32F103Rx
Text: STM32F103x6 STM32F103x8 STM32F103xB Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces Features • ■ ■ Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F103x6
STM32F103x8
STM32F103xB
32-bit
16-bit
4-to-16
stm32f103xx
STM32F103Tx
STM32 LQFP-64 footprint
FT2384
LQFP100
LQFP48
LQFP64
STM32F103C6
STM32F103C8
STM32F103Rx
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bq24730
Abstract: bq24730RGFR bq24730RGFT FDS6680A SI4435 BAT54 BAT54C p-channel mosfet driver
Text: bq24730 www.ti.com SLUS695 – MARCH 2006 ADVANCED MULTI-CHEMISTRY AND MULTI-CELL SYNCHRONOUS SWITCH-MODE CHARGER AND SYSTEM POWER SELECTOR FEATURES APPLICATIONS • • • • REGN LODRV PGND STAT 36 35 34 33 HIDRV PH 38 37 PVCC BTST 32 CELLS 2 31 BATDRV
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bq24730
SLUS695
bq24730RGFR
bq24730RGFT
FDS6680A
SI4435
BAT54
BAT54C
p-channel mosfet driver
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HXM122032-GB1
Abstract: HXM122032-GB1TM HXM122032 pjs008-2000 STM8A STM8 spi display AN2673 notes on USART communication 78EEUD lcd display
Text: AN2673 Application note STM8A SPI application examples Introduction This application note is one of a set of application notes giving examples of how to use the various blocks of the STM8A microcontroller family and the STM8 firmware library. It is intended to provide three practical application examples of the use of the SPI peripheral in
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AN2673
HXM122032-GB1
HXM122032-GB1TM
HXM122032
pjs008-2000
STM8A
STM8 spi display
AN2673
notes on USART communication
78EEUD
lcd display
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STM32F103Cx
Abstract: C4496 STM32F103CBT6 STM32F103XX TFBGA-64 TFBGA64 STM32F103xE STM32F103C8 stm32f10x manual BGA64
Text: STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces Features • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
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STM32F103x8
STM32F103xB
32-bit
4-to-16
STM32F103Cx
C4496
STM32F103CBT6
STM32F103XX
TFBGA-64
TFBGA64
STM32F103xE
STM32F103C8
stm32f10x manual
BGA64
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TL431ACDR
Abstract: TL431ACDBVR TL431 TL431A TL431B TL431CD TL431CP TL432 TL432A TL432B
Text: TL431, TL431A, TL431B TL432, TL432A, TL432B ADJUSTABLE PRECISION SHUNT REGULATORS SLVS543J − AUGUST 2004 − REVISED DECEMBER 2005 D Operation From −40°C to 125°C D Reference Voltage Tolerance at 25°C D − 0.5% . . . B Grade − 1% . . . A Grade − 2% . . . Standard Grade
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TL431,
TL431A,
TL431B
TL432,
TL432A,
TL432B
SLVS543J
TL431B)
TL431ACDR
TL431ACDBVR
TL431
TL431A
TL431B
TL431CD
TL431CP
TL432
TL432A
TL432B
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Untitled
Abstract: No abstract text available
Text: 2 THIS DRAWI NG IS UNPUBLISHED. C O P Y R I G H T 20 R E L E A S E D FOR P U B L I C A T I O N BY TYCO E L E C T R O N I C S C O R P O R A T I O N . A L L 20 LOC 00 GP R 1G H T S R E S E RV E D. DI M DI M TT — ^ REF ITTTT1 ITTTT1 ED ITTTT1 DIB DIB ] [ ]] [ ]] [ ]] [ ]] [ ]] [
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OCR Scan
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14MAY2006
14MAR2008
06MAY2008
13MAY2008
I3038
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