Contextual Info: * 3-BIT SCANNABLE REGISTERED BUS e V A IC D ^ U S w N C n G w SEMICONDUCTOR SY10E337 SY100E337 T R A N Q P F IV F R n A N o U tlv tn FEATURES DESCRIPTION 1500ps max. clock to bus data transmit 1000ps max. clock to Q (data receive) Extended 100E V ee range of -4.2V to -5.5V

Contextual Info: * S Y 1 0 4 8 4 -8 4K x 4 ECL RAM SYNERGY S Y 1 0 4 8 4 -1 0 SEMICONDUCTOR DESCRIPTION FEATURES • Address access time, tAA: 8/10ns max. ■ Chip select access time, tAc: 4/5ns max. ■ Write pulse width, tww: 10ns min. ■ Choice of two edge rates tr/tf : 500 or 1500ps (typ.)

Contextual Info: 'j•BIT R E G i S i E R F i SYNERGY T R A N S C E IVi-iR fliC O N D U C 7 Oh ■ 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transm it and receive registers with separate clocks ■ 1500ps max. delay from C L K i to Bus Outputs BUS ■ 1500ps max. delay from CLK 2 to Receiver Outputs

Contextual Info: FEATURES DESCRIPTION • 251 i cutoff bus output ■ Extended 100E V ee range of -4 .2 V to -5 .5 V ■ 50£2 receiver output ■ Transm it and receive registers ■ 1500ps max. clock to bus ■ 10OOps max. clock to Q ■ Internal edge slow-down capacitors on bus outputs

SY100S891

Abstract: SY100S891JC SY100S891JCTR
Contextual Info: Micrel, Inc. 5-BIT REGISTERED TRANSCEIVER FEATURES SY100S891 SY100S891 DESCRIPTION 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs (Q)

Contextual Info: * 3-BIT REGISTERED BUS TRANSCEIVER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ ■ ■ ■ ■ 25£2 cutoff bus output 50£2 receiver output Transmit and receive registers 1500ps max. clock to bus 1000ps max. clock to Q Internal edge slow-down capacitors on bus outputs

TO220V

Contextual Info: « 5-BIT REGISTERED TRANSCEIVER SYNERGY SY100S891 SEMICONDUCTOR FEATURES DESCRIPTION 25 ohm cut-off bus outputs 50 ohm receiver outputs Transm it and receive registers w ith separate clocks 1500ps max. delay from C LKi to Bus O utputs BUS 1500ps max. delay from CLK 2 to Receiver O utputs

Contextual Info: * 5-BIT REGISTERED TRANSCEIVER SYNERGY SY100S891 SEMICONDUCTOR DESCRIPTION FEATURES • 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transmit and receive registers with separate clocks ■ 1500ps max. delay from CLKi to Bus Outputs BUS ■ 1500ps max. delay from CLK2 to Receiver Outputs

F100K

Abstract: SY100S366 SY100S366DC SY100S366FC
Contextual Info: * SYNERGY 9-BIT COMPARATOR SV100S366 S E M IC O N D U C T O R DESCRIPTION FEATURES Max. propagation delay of 1500ps Ie e min. of-120m A ESD protection of 2000V Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for

SY100E336

Abstract: SY10E336
Contextual Info: * 3-BIT REGISTERED BUS TRANSCEIVER SYNERGY S E M IC O N D U C T O R FEATURES SY10E336 SY100E336 DESCRIPTION I 25Q cutoff bus output I Extended 100E V ee range of -4 .2 V to -5 .5 V I 5012 receiver output I Transm it and receive registers I 1500ps max. clock to bus

Contextual Info: * -BIT C O M P A R A T O ? SYN ER G Y M10S366 S E M IC O N D U C T O R DESCRIPTION FEATURES • Max. propagation delay of 1500ps ■ Ie e min. of-120m A ■ Industry standard 100K ECL levels ■ Extended supply voltage option: V ee = -4.2V to -5.5V The SY100S366 is an ultra-fast 9-bit m agnitude

Contextual Info: FEATURES D E S C R IP T IO N • 1500ps max. clock to bus data transmit ■ "IQOOps max. clock to Q (data receive) ■ Extended 100E Vee range of -4.2V to -5.5V ■ 25Q cutoff bus outputs ■ 50 n receiver outputs ■ Scannable implementation of E336 ■ Synchronous and asynchronous bus enables

Contextual Info: 5-BIT REGISTERED TRANSCEIVER FEATURES SY100S891 DESCRIPTION 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs (Q)

SY100E336

Abstract: SY10E336 SY10E336JC
Contextual Info: FEATURES 25Ω cutoff bus output Extended 100E VEE range of –4.2V to –5.5V 50Ω receiver output Transmit and receive registers 1500ps max. clock to bus 1000ps max. clock to Q Internal edge slow-down capacitors on bus outputs Additional package ground pins

Contextual Info: * e v w 3 -B IT S C A N N A B L E R E G IS T E R E D B U S T R A N S C E IV E R 1" A N i i O t l V t H c o /'v SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES 1500ps max. clock to bus data transm it 1000ps max. clock to Q (data receive) Extended 100E V ee range of -4 .2 V to -5 .5 V

Contextual Info: « 5-BIT REGISTERED TRANSCEIVER SYNER G Y SY100S891 SEMICONDUCTOR FEATURES DESCRIPTION • 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transmit and receive registers with separate clocks ■ 1500ps max. delay from CLKi to Bus Outputs BUS ■ 1500ps max. delay from CLK2 to Receiver Outputs

Contextual Info: * 5-BIT REGISTE RED TR AN SCEIVER SYNERGY SEMICONDUCTOR FEATURES SY100S891 DESCRIPTION • 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transmit and receive registers with separate clocks ■ 1500ps max. delay from CLKi to Bus Outputs BUS ■ 1500ps max. delay from CLK2 to Receiver Outputs

Contextual Info: * 3-BIT REGISTERED BUS TRANSCEIVER SYNERGY SEMICONDUCTOR FEATURES SY10E336 SY100E336 DESCRIPTION • 25Q. cutoff bus output ■ Extended 100E V ee range of -4.2V to -5.5V ■ 50£! receiver output ■ Transmit and receive registers ■ 1500ps max. clock to bus

Contextual Info: « 5-BIT REGISTERED TRANSCEIVER SYNER G Y SY100S891 SEMICONDUCTOR FEATURES DESCRIPTION • 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transmit and receive registers with separate clocks ■ 1500ps max. delay from CLKi to Bus Outputs BUS ■ 1500ps max. delay from CLK2 to Receiver Outputs

Contextual Info: * 3-BIT REGISTERED BUS TRANSCEIVER SYNERGY SEMICONDUCTOR FEATURES SY10E336 SY100E336 DESCRIPTION • 250. cutoff bus output ■ Extended 100E V ee range of -4 .2 V to -5 .5 V ■ 5012 receiver output ■ Transm it and receive registers ■ 1500ps max. clock to bus

Contextual Info: * 3-BIT SCANNABLE REGISTERED BUS e V A IC D ^ U S w N C n G w SEMICONDUCTOR SY10E337 SY100E337 T R A N Q P F IV F R n A N o U tlv tn FEATURES DESCRIPTION 1500ps max. clock to bus data transmit 1000ps max. clock to Q (data receive) Extended 100E V ee range of -4.2V to -5.5V

SY100E336

Abstract: SY10E336 SY10E336JC SY10E336JCTR 1q50
Contextual Info: 3-BIT REGISTERED BUS TRANSCEIVER FEATURES DESCRIPTION 25Ω cutoff bus output Extended 100E VEE range of –4.2V to –5.5V 50Ω receiver output Transmit and receive registers 1500ps max. clock to bus 1000ps max. clock to Q Internal edge slow-down capacitors on bus outputs

E336

Abstract: SY100E337 SY10E337
Contextual Info: A 3-BIT SCANNABLE SYNERGY t r a n s c b v e r BUS S E M IC O N D U C T O R 1 DESCRIPTION FEATURES 1500ps max. clock to bus data transmit 10OOps max. clock to Q (data receive) Extended 100E V ee range of -4.2V to -5.5V 25Q cutoff bus outputs 50£2 receiver outputs

PS 1025

Abstract: SY100S891 SY100S891JC SY100S891JCTR
Contextual Info: * 5-BIT REGISTERED TRAN SC EIVER SYNERGY SY100S891 S E M IC O N D U C T O R DESCRIPTION FEATURES 25 ohm cut-off bus outputs 50 ohm receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK 1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs