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    Untitled

    Abstract: No abstract text available
    Text: MAX24101 15Gbps Octal Linear Equalizer General Description The MAX24101 restores high-frequency signal level at the decision-feedback equalizer DFE receiver for highloss backplane and cable channels. This permits the DFE receiver to meet BER goals. At 15Gbps, the MAX24101


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    MAX24101 15Gbps MAX24101 15Gbps, PDF

    "higig header"

    Abstract: higig specification higig protocol overview TN1154 cx4 to sma BCM56802 higig pause frame ir9216 BROADCOM higig2
    Text: LatticeSC/M Broadcom HiGig+ 12 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1154 Introduction This technical note describes a physical layer HiGig+ 12 Gbps interoperability test between a LatticeSC/M device and the Broadcom BCM56802 network switch. The test was limited to the physical layer up to XGMII of the 10


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    TN1154 BCM56802 1-800-LATTICE "higig header" higig specification higig protocol overview TN1154 cx4 to sma higig pause frame ir9216 BROADCOM higig2 PDF

    ARM11 processor block diagram

    Abstract: ARM11 processor NFP-3240
    Text: SiNFP-32xx Flow Processor: Ruggedized Netronome NFP; 133 MHz DDR3 Product Highlights • Source-code compatibility including backwards-compatibility with Intel IXP28XX microengines for customer application migration • High-performance solution with low power consumption for a broad


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    SiNFP-32xx IXP28XX Mpps/20 70-million 64-byte SiNFP-3224-0-A2-BM10 SiNFP-3224-0-A2-CM10 SiNFP-3224-0-A2-DM10 SiNFP-3224-8-A2-AM10 SiNFP-3224-8-A2-BM10 ARM11 processor block diagram ARM11 processor NFP-3240 PDF

    IXP2800

    Abstract: ixp2400 rohs Intel IXA SDK Developers Workbench D-128 intel ixa sdk core components ixa sdk IXP2400 IXP2800 microengine
    Text: product brief Intel IXP2800 Network Processor For OC-192/10 Gbps network edge and core applications Product Highlights • Delivers 10 Gbps packet forwarding and traffic management on a single chip ■ Introduces Hyper Task Chaining processing technology that enables deep packet


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    IXP2800 OC-192/10 32-bit 46-byt ixp2400 rohs Intel IXA SDK Developers Workbench D-128 intel ixa sdk core components ixa sdk IXP2400 IXP2800 microengine PDF

    88E3082

    Abstract: Marvell prestera 88E3083 Prestera 88 Marvell Marvell prestera 98 Marvell PHY register map Marvell prestera-ex MARVELL 88 98MX620
    Text: Marvell Technology Restricted Document Do Not Reproduce Pre-release Draft This is the html version of the file . G o o g l e automatically generates html versions of documents as we crawl the web.


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    98MX610 98MX620 98MX630 98mx610 98MX610/620/630 48-Port 88E3082 Marvell prestera 88E3083 Prestera 88 Marvell Marvell prestera 98 Marvell PHY register map Marvell prestera-ex MARVELL 88 PDF

    3com superstack

    Abstract: Crossbar Switches 1000BASE-X 100BASE-FX 28115 "Spanning Tree"
    Text: Performance Optimized Ethernet Switching Lucent Technologies’ Crossbar Switch Architecture: Performance-Optimized Ethernet Switching Abstract Crossbar switches offer substantial benefits in performance scaling when compared with shared memory and shared bus architecture switches. This is because with a crossbar switch,


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    PDF

    higig2 frame format

    Abstract: "higig header" EZchip higig2 higig specification verilog code for spi4.2 to fifo higig pause frame marvell 618 datasheet pt36C 0x00900
    Text: LatticeSCM XAUI to SPI4.2 July 2008 Reference Design RD1033 Introduction The XAUI to SPI4.2 X2S4 Bridge reference design is a cost-effective system solution for bridging SPI4.2 based network processors and 10G/10G+ Ethernet switching devices. On the XAUI side, the X2S4 optionally supports the


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    RD1033 10G/10G+ 12Gbps RD1033. higig2 frame format "higig header" EZchip higig2 higig specification verilog code for spi4.2 to fifo higig pause frame marvell 618 datasheet pt36C 0x00900 PDF

    CN6880

    Abstract: 40GBASE-KR4 CN6880-1200 10GBASE-BX4 40GBASE-KR interlaken network processor Cavium Octeon II octeon octeon plus CAVIUM
    Text: ATCA-9405 AdvancedTCA 40G Packet Processing Blade PRELIMINARY DATA SHEET Ideal for high touch and high throughput packet processing applications to support the latest data-intensive network evolution ƒƒ PICMG compliant single-slot AdvancedTCA® blade with


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    ATCA-9405 1/10G/40G CN6880 MIPS64 10GbE 40GbE ATCA9405-D1 40GBASE-KR4 CN6880-1200 10GBASE-BX4 40GBASE-KR interlaken network processor Cavium Octeon II octeon octeon plus CAVIUM PDF

    20/kd 5810

    Abstract: kd 5810
    Text: 3 _sz_ 4 3M HIGH SPEED CARD-EDGE CONNECTOR, SPD08 SERIES FIG. 1 FOR POSITIONS 020, 040, 060, W/O LATCH TYPE SHOWN: S PD 08-020-X X -TR DATE CODE YWWD=DATE OF MANUFACTURE A 06mm ADHESIVE POSITIONS DIMENSIONS


    OCR Scan
    SPD08 08-020-X 20/kd 5810 kd 5810 PDF