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    16 MACROCELL Search Results

    16 MACROCELL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    EP610DM-30 Rochester Electronics LLC EP610 - Classic Family EPLD, Logic,300 Gates,16 Macrocells Visit Rochester Electronics LLC Buy
    EP910LI-30-G Rochester Electronics LLC EP910 - Classic Family EPLD, Logic,450 Gates,24 Macrocells Visit Rochester Electronics LLC Buy
    EP610LI-25 Rochester Electronics LLC EP610 - Classic Family EPLD, Logic,300 Gates,16 Macrocells Visit Rochester Electronics LLC Buy
    EP610LI-30 Rochester Electronics LLC EP610 - Classic Family EPLD, Logic,300 Gates,16 Macrocells Visit Rochester Electronics LLC Buy
    EP910PI-30 Rochester Electronics LLC EP910 - Classic Family EPLD, Logic,450 Gates,24 Macrocells Visit Rochester Electronics LLC Buy

    16 MACROCELL Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    4-bit even parity using mux 8-1

    Abstract: full subtractor implementation using NOR gate 4096 bit RAM 74 full subtractor full subtractor using mux
    Text: Introduction to Delta39K’s Carry Chain Introduction VCC VCC GCLK[3:0] Logic Block PIM 16 16 Logic Block PIM 39 39 Logic Block PIM 16 16 Logic Block PIM 39 39 Logic Block PIM 16 16 Logic Block PIM 39 39 Logic Block PIM 16 16 Logic Block PIM 39 23 Cluster Memory PIM


    Original     		Delta39K Delta39K, Ultra37000. Ultra37128 4-bit even parity using mux 8-1 full subtractor implementation using NOR gate 4096 bit RAM 74 full subtractor full subtractor using mux PDF

    vhdl code for 8-bit serial adder

    Abstract: dse1 D950-CORE ieee floating point alu in vhdl vhdl code for 16 bit barrel shift register vhdl code for 8-bit adder
    Text: D950-CORE 16-Bit Fixed Point Digital Signal Processor DSP Core • ■ ■ ■ ■ OUTPUT CLOCKS 16 XA-bus 16 YA-bus 16 CALCULATION 16 UNIT PROGRAM CONTROL UNIT 3 ID-bus 16 IA-bus 16 DATA MEMORY 6 ADDRESS PROGRAM MEMORY ■ UNIT VDD VSS ■ DATA CALCULATION


    Original     		D950-CORE 16-Bit 16-ights vhdl code for 8-bit serial adder dse1 D950-CORE ieee floating point alu in vhdl vhdl code for 16 bit barrel shift register vhdl code for 8-bit adder PDF

    8 bit barrel shifter vhdl code

    Abstract: vhdl code for 8-bit serial adder D950-CORE vhdl code for SIGNED MULTIPLIER accumulator vhdl code for 8-bit adder Ya14
    Text: D950-CORE 16-Bit Fixed Point Digital Signal Processor DSP Core • ■ ■ ■ ■ OUTPUT CLOCKS 6 16 XA-bus 16 YA-bus 16 CALCULATION 16 UNIT PROGRAM CONTROL UNIT 3 ID-bus 16 IA-bus 16 DATA MEMORY ADDRESS PROGRAM MEMORY ■ UNIT VDD VSS ■ DATA CALCULATION


    Original     		D950-CORE 16-Bit 16-bihts 8 bit barrel shifter vhdl code vhdl code for 8-bit serial adder D950-CORE vhdl code for SIGNED MULTIPLIER accumulator vhdl code for 8-bit adder Ya14 PDF

    39a132

    Abstract: d950 BSU60 vhdl code lte vhdl code for SIGNED MULTIPLIER accumulator D950CORE D950-CORE 4 bit barrel shifter using mux YA11 vhdl code for 16 bit barrel shifter
    Text: D950-CORE 16-BIT FIXED POINT DIGITAL SIGNAL PROCESSOR DSP CORE PRODUCT PREVIEW • ■ ■ ■ ■ ■ ADDRESS OUTPUT CLOCKS 6 16 XA-bus 16 CALCULATION 16 UNIT YA-bus PROGRAM CONTROL UNIT 16 3 ID-bus IA-bus 16 16 DATA MEMORY YD-bus XD-bus UNIT VDD VSS ■


    Original     		D950-CORE 16-BIT 40-BIT 39a132 d950 BSU60 vhdl code lte vhdl code for SIGNED MULTIPLIER accumulator D950CORE D950-CORE 4 bit barrel shifter using mux YA11 vhdl code for 16 bit barrel shifter PDF

    4512c

    Abstract: ispMACH lc4064v LC4032 LC4032V-10TN48I 4032V 4000ZC LC4384V-35TN176C LC4512V-5FN256I LC4128V-5T128C LC4512V
    Text: Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 16 16 Generic Logic Block 36 I/O Block ORP 16 36 16 16 36 36 Generic 16 Logic Block VCCO1 GND TCK TMS TDI TDO VCC GND GOE0 GOE1 16 I/O Bank 0 ORP Generic Logic Block I/O Block ORP I/O Bank 1 I/O Block


    Original     		000V/B/C/Z LC4256V-75TN176E LC4256V-75TN144E LC4256V-75TN100E LC4256V LC4128V-75TN100E LC4128V LC4128V-75TN144E TN1004) 4512c ispMACH lc4064v LC4032 LC4032V-10TN48I 4032V 4000ZC LC4384V-35TN176C LC4512V-5FN256I LC4128V-5T128C LC4512V PDF

    ARM processor

    Abstract: ARM processor fundamentals ARM processor pin configuration ARM7500 LA-1931 la1628 BD 176
    Text: 1 16 11 Clocks, Power Saving, and Reset 16.1 Clock control 16-2 16.2 Power management 16-3 16.3 Reset 16-6 ARM7500 Data Sheet ARM DDI 0050C Preliminary - Unrestricted This chapter describes clock control, power management, and reset. 16-1 Clocks, Power Saving, and Reset


    Original     		ARM7500 0050C 32MHz, ARM processor ARM processor fundamentals ARM processor pin configuration LA-1931 la1628 BD 176 PDF

    ARM7500FE

    Abstract: ARM FPA DRAM Controller 08FF
    Text: 1 11 Memory and I/O Programmers’ Model 16 This chapter details the programmable registers for the memory and I/O subsystem. 16.1 Introduction 16-2 16.2 Summary of Registers 16-2 16.3 Register Description 16-6 ARM7500FE Data Sheet ARM DDI 0077B Open Access - Preliminary


    Original     		ARM7500FE 0077B ARM FPA DRAM Controller 08FF PDF

    Untitled

    Abstract: No abstract text available
    Text: UM10524 LPC1315/16/17/45/46/47 User manual Rev. 4 — 12 March 2013 User manual Document information Info Content Keywords LPC1315/16/17/45/46/47, ARM Cortex-M3, microcontroller, USB Abstract LPC1315/16/17/45/46/47 User manual UM10524 NXP Semiconductors LPC1315/16/17/45/46/47 User manual


    Original     		UM10524 LPC1315/16/17/45/46/47 LPC1315/16/17/45/46/47, 0x4003 PDF

    80c196 application note

    Abstract: No abstract text available
    Text: PSD4235G2V Flash in-system programmable ISP peripherals for 16-bit MCUs (3.3 V supply) Features PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/Os: • ■ 64 Kbit SRAM ■ PLD with macrocells


    Original     		PSD4235G2V 16-bit 80c196 application note PDF

    HVGA 480X320

    Abstract: 480X272
    Text: PSoC Creator Component Datasheet Graphic LCD Controller GraphicLCDCtrl 1.70 Features • Fully programmable screen size support up to HVGA resolution including:  QVGA (320x240) @ 60 Hz 16 bpp  WQVGA (480x272) @ 60 Hz 16 bpp  HVGA (480x320) @ 60 Hz 16 bpp


    Original     		320x240) 480x272) 480x320) 23-bit 16-bit HVGA 480X320 480X272 PDF

    Untitled

    Abstract: No abstract text available
    Text: LPC2420/2460 Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 6.2 — 16 October 2013 Product data sheet 1. General description NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit


    Original     		LPC2420/2460 16-bit/32-bit LPC2420/2460 16-bit/32-bit 32-bit 16-bit LPC2420 PDF

    LPC2000

    Abstract: LPC2468 LPC2468FBD208 LPC2468FET208 LQFP208 TFBGA208
    Text: LPC2468 Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 02 — 16 October 2007 Preliminary data sheet 1. General description NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit


    Original     		LPC2468 16-bit/32-bit LPC2468 16-bit/32-bit 128-bit LPC2000 LPC2000 LPC2468FBD208 LPC2468FET208 LQFP208 TFBGA208 PDF

    EP600

    Abstract: 5c060 P5C060-55 intel PLD EP600 programming D5C060-45
    Text: in t e i 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 16 Macrocells with Programmable I/O Architecture; up to 20 Inputs 4 Dedicated, 16 I/O or 16 Outputs ■ Programmable Output Registers can be


    OCR Scan     		5C060 16-MACROCELL 5C060 5C060-45 EP600 P5C060-55 intel PLD EP600 programming D5C060-45 PDF

    Untitled

    Abstract: No abstract text available
    Text: EP600 EPLD t i d = n & 16-Macrocell Device \ June 1993, ver. 1 Data Sheet Supplement 16-macrocell Classic EPLD - Combinatorial speeds with tPD = 45 ns Counter frequencies up to 222 MHz Pipelined data rates up to 263 MHz □ Programmable I/O architecture with up to 20 inputs or 16 outputs


    OCR Scan     		EP600 16-Macrocell EP610, EP610A, EP610T, EP630 PDF

    Untitled

    Abstract: No abstract text available
    Text: % Micro Linear FB300 Tile Arrav Family Description FB324 Bipolar Tile Array The FB324 has 6 general purpose tiles and 16 high performance tiles. The six general purpose tiles can use any of the predefined macrocells from the FB300 family. The 16 high performance tiles support higher


    OCR Scan     		FB300 FB324 FB324â MLCH300 PDF

    AMD 685

    Abstract: cascode transistor array 5K02 tiles ecl 10K signetics FB300 FB324
    Text: 1%, Micro Linear FB324 BIPOLAR TILE ARRAY FB300 Tile Arrav Family Description The FB324 has 6 general purpose tiles and 16 high performance tiles. The six general purpose tiles can use any of the predefined macrocells from the FB300 family. The 16 high performance tiles support higher


    OCR Scan     		FB300 FB324 FB324 MLCH300 GG/CS-5K-02/88 AMD 685 cascode transistor array 5K02 tiles ecl 10K signetics PDF

    EP600

    Abstract: EP600 eprom 5c060 P5C060-45 EP600 programming 5C060-55 5C06055 EP6003 16-MACROCELL 74HC
    Text: intJ. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O


    OCR Scan     		5C060 5C060-45 130pF EP600 EP600 eprom 5c060 P5C060-45 EP600 programming 5C060-55 5C06055 EP6003 16-MACROCELL 74HC PDF

    Untitled

    Abstract: No abstract text available
    Text: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins


    OCR Scan     		EP610 16-macrocell EP610, EP610I, EP600I 24-pin 16-bit PDF

    Untitled

    Abstract: No abstract text available
    Text: EP610A EPLD AN b r ^ n ^ \ High-Performance 16-Macrocell Device March 1993, ver. 2 Data Sheet Supplement □ Features □ □ □ P re lim in a ry Inform ation □ □ □ □ □ □ Highest-performance 16-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns


    OCR Scan     		EP610A 16-Macrocell EP610 EP610T EP610 16-Macrocell PDF

    ALTERA EP610

    Abstract: MIL-STD-883-compliant
    Text: EP610 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 35 ns Counter frequencies up to 28.5 MHz Pipelined data rates up to 37 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs


    OCR Scan     		EP610 MIL-STD-883-Compliant 16-macrocell 24-pin 16-bit MIL-STD-883-Compliant ALTERA EP610 PDF

    Multiplexers

    Abstract: 5C060 5C060-55 EP600 programming 5C060-45 EP600 P5C060-55 intel PLD
    Text: in t e i. 5C060 16-MACROCELL CMOS PLD • High-Performance LSI Semi-Custom Logic Alternative to Low-End Gate Arrays, TTL, and 74HC SSI and MSI Logic ■ 8 P-Terms, Selectable SOP Invert, Clear and OE P-Terms for Each Macrocell ■ 16 Macrocells with Programmable I/O


    OCR Scan     		5C060 16-MACROCELL Gener60 25MHz 5C060-45 Multiplexers 5C060-55 EP600 programming EP600 P5C060-55 intel PLD PDF

    fxz 556

    Abstract: EP6101-10 EP610 pipelined adder EP610-Z5 EP610-30 EP610-35 EP610-25 EP610-15 EP610-20
    Text: EP6 1 0 EPLD High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins


    OCR Scan     		16-macrocell EP610 EP610I 24-pin 28-pin 16-bit fxz 556 EP6101-10 pipelined adder EP610-Z5 EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 PDF

    EP610

    Abstract: MIL-STD-883-compliant TI EP610 EP610-15 PALCE610 altera ep610 ALTERA MAX 5000 programming EP610-20 EP610I
    Text: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 Clock pins


    OCR Scan     		EP610 16-macrocell EP610, EP610I, EP610T, MIL-STD-883-compliant, EP600I, PALCE610 24-pin MIL-STD-883-compliant TI EP610 EP610-15 altera ep610 ALTERA MAX 5000 programming EP610-20 EP610I PDF

    EP61Q-15

    Abstract: EP61B EP610-30 EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
    Text: EP610 EPLD Features • ■ ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs


    OCR Scan     		EP610 16-macrocell EP610I 24-pin 28-pin 16-bit EP61Q-15 EP61B EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP6101-10 PDF