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    16 STAGE PIPELINE Search Results

    16 STAGE PIPELINE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    4015A/BEA Rochester Electronics LLC 4015A - Shift Register, Dual 4-Stage - Dual marked (M38510/05703BEA) Visit Rochester Electronics LLC Buy
    4031A/BEA Rochester Electronics LLC 4031A - Shift Register, 64-Stage Static - Dual marked (M38510/05705BEA) Visit Rochester Electronics LLC Buy
    4015A/BFA Rochester Electronics LLC 4015A - Shift Register, Dual 4-Stage - Dual marked (M38510/05703BFA) Visit Rochester Electronics LLC Buy
    29FCT520ALB Renesas Electronics Corporation MULTI-LEVEL PIPELINE REG Visit Renesas Electronics Corporation
    29FCT520ATQ8 Renesas Electronics Corporation MULTI-LEVEL PIPELINE REG Visit Renesas Electronics Corporation

    16 STAGE PIPELINE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: High Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate AD9260 STAGE 1:2X 16-BIT: DECIMATION 10MHz FILTER REFERENCE BUFFER DRVDD DRVSS DIGITAL DEMODULATOR 12-BIT: 20MHz AD9260 STAGE 2:2X 16-BIT: DECIMATION 5MHz FILTER OTR 16-BIT: STAGE 3:2X


    Original     		PDF 16-Bit AD9260 16-BIT: 10MHz 12-BIT: 20MHz AD9260

    diode T35 12H

    Abstract: 100NS PQFP144 ST10F167 ST10F167 Controller disassembler st10 Bootstrap
    Text: ST10F167 16-BIT MCU WITH 128KBYTE FLASH MEMORY • HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE. – 16-BIT CPU WITH 4 STAGE PIPELINE – 100NS INSTRUCTION CYCLE TIME AT 20MHz CPU CLOCK – 500NS MULTIPLICATION 16*16 BIT – 1µS DIVISION (32/16 BIT)


    Original     		PDF ST10F167 16-BIT 128KBYTE 100NS 20MHz 500NS diode T35 12H PQFP144 ST10F167 ST10F167 Controller disassembler st10 Bootstrap

    74HC245 application

    Abstract: ad780r 100k trimpot pin configuration 1K variable resistor pin configuration transistor 2N2222 AD9260-EB PIN CONFIGURATION 2N2222 AD9260 ttl buffer 74hc245 star delta ladder diagram
    Text: High Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate AD9260 STAGE 1:2X 16-BIT: DECIMATION 10MHz FILTER REFERENCE BUFFER DRVDD DRVSS DIGITAL DEMODULATOR 12-BIT: 20MHz AD9260 STAGE 2:2X 16-BIT: DECIMATION 5MHz FILTER OTR 16-BIT: STAGE 3:2X


    Original     		PDF 16-Bit AD9260 16-BIT: 10MHz 12-BIT: 20MHz AD9260 74HC245 application ad780r 100k trimpot pin configuration 1K variable resistor pin configuration transistor 2N2222 AD9260-EB PIN CONFIGURATION 2N2222 ttl buffer 74hc245 star delta ladder diagram

    L29C520

    Abstract: LPR520 LPR520JC25 LPR520PC15 LPR520PC22 LPR520PC25 y10 smd
    Text: LPR520 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register


    Original     		PDF LPR520 16-bit MIL-STD-883, 40-pin 44-pin L29C520 LPR520 LPR520JC25 LPR520PC15 LPR520PC22 LPR520PC25 y10 smd

    L29C520

    Abstract: LPR520 LPR520JC15 LPR520JC22
    Text: LPR520 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register


    Original     		PDF LPR520 16-bit LPR520 L29C520 16-bit LPR520JC15 LPR520JC22

    LPR520

    Abstract: LPR520JC22 L29C520
    Text: LPR520 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register


    Original     		PDF LPR520 16-bit LPR520 L29C520 16-bit LPR520JC22

    Untitled

    Abstract: No abstract text available
    Text: LPR520/521 LPR520/521 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline


    Original     		PDF LPR520/521 16-bit LPR520 LPR521 IDT29FCT520/ IDT29FCT521 Am29520/ Am29521

    SUSCON capacitor

    Abstract: ST10F168-Q3 transmitter circuit in GPR st10f168s SUSCON PQFP144 ST10F168 diode T35 12H st10 Bootstrap
    Text: ST10F168 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE – 80ns INSTRUCTION CYCLE TIME AT 25MHz CPU CLOCK – 400ns 16 X 16-BIT MULTIPLICATION – 800ns 32 / 16-BIT DIVISION – ENHANCED BOOLEAN BIT MANIPULATION


    Original     		PDF ST10F168 16-BIT 25MHz 400ns 800ns F168Q3Q6 SUSCON capacitor ST10F168-Q3 transmitter circuit in GPR st10f168s SUSCON PQFP144 ST10F168 diode T35 12H st10 Bootstrap

    Untitled

    Abstract: No abstract text available
    Text: LPR520 □ FV IC E S IN C O R P Q R A T F D FEATURES 4 x 16-bit Multilevel Pipeline Register DESCRIPTION □ Four 16-bit Registers □ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register The LPR520 is functionally compat­ ible with the L29C520 but have 16-bit


    OCR Scan     		PDF LPR520 16-bit LPR520 L29C520 40-pin 44-pin LPR520JC22

    L1823

    Abstract: DI437 smd diode Y5
    Text: L Q G / C L P R 5 2 0 4 x 16-bit Multilevel Pipeline Register DRVICES INCORPORATED FEATURES_j □ Four 16-bit Registers □ Im plem ents Double 2-Stage Pipe­ line or Single 4-Stage Pipeline •Register □ H old, Shift, and Load Instructions


    OCR Scan     		PDF LPR520 16-bit MIL-STD-883, 40-pin 44-pin L29C520 L1823 DI437 smd diode Y5

    Untitled

    Abstract: No abstract text available
    Text: 4 x 16-bit Multilevel FEATURES □ Four 16-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, Load Instructions □ Separate Data In and Data Out Pins □ High Speed, Low Power CMOS Technology □ Three-State Outputs


    OCR Scan     		PDF 16-bit LPR520 LPR521 AM29520 AM29521 LPR520,

    Untitled

    Abstract: No abstract text available
    Text: LPR520 D E V IC E S IN C O R P O R A T E D FEATURES 4 x 16-bit Multilevel Pipeline Register DESCRIPTION □ Four 16-bit Registers □ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register The L P R 520 is functionally compat­ ible with the L29C520 but have 16-bit


    OCR Scan     		PDF LPR520 16-bit L29C520 16-bit LPR520 44-pin 520JC

    Untitled

    Abstract: No abstract text available
    Text: LPR520/521 4 x 16-bit Multilevel Pipeline Register V IC I S INCORPORA ILL DESCRIPTION FEATURES □ Four 16-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, and Load Instructions □ Separate Data In and Data Out Pins


    OCR Scan     		PDF LPR520/521 16-bit MIL-STD-883, 40-pin 44-pin LPR520 LFR521

    Untitled

    Abstract: No abstract text available
    Text: LPR520/521 4 x 16-bit Multilevel Pipeline Register DESCRIPTION FEATURES □ Four 16-bit R egisters □ Im plem ents D ouble 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ H old, Shift, and L oad Instructions □ Separate D ata In an d D ata O ut Pins


    OCR Scan     		PDF LPR520/521 16-bit MIL-STD-883, 40-pin 44-pin LPR520 LPR521

    y10 smd

    Abstract: PR521
    Text: LPR520/521 4 x 16-bit Multilevel Pipeline Register Üfc.VlO t-S IN C O R P O R A I L U DESCRIPTION FEATURES □ Four 16-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, and Load Instructions □ Separate Data In and Data Out Pins


    OCR Scan     		PDF LPR520/521 16-bit MIL-STD-883, 40-pin 44-pin LPR520 LFR521 y10 smd PR521

    Untitled

    Abstract: No abstract text available
    Text: ST10F167 16-bit MCU with 128KByte FLASH memory DATASHEET High Performance CPU • 16-bit CPU with 4 stage pipeline • 100ns instruction cycle time at 20MHz CPU clock • 500ns multiplication 16*16 bit • 1(as division (32/16 bit) • Enhanced boolean bit manipulation


    OCR Scan     		PDF ST10F167 16-bit 128KByte 100ns 20MHz 500ns 20MHz

    Untitled

    Abstract: No abstract text available
    Text: SCS-THOMSON *JM > DSll g|g@ilUl inMID @ ST10R163 16-BIT ROMLESS MICROCONTROLLER DATASHEET High performance 16-bit CPU with 4-stage pipeline 80ns instruction cycle time at 25-MHz CPU clock 400 ns multiplication (16 x 16 bits , 800 ns division (32 /1 6 bit)


    OCR Scan     		PDF ST10R163 16-BIT 25-MHz TQFP100 ST10R163BT1

    Untitled

    Abstract: No abstract text available
    Text: CFB2402A CFB2402A MPY - 1PL GENERAL DESCRIPTION: 16 X 16 TWO’S COMP PLAIN MPY, 1-STAGE PIPELINE, CS CFB2402A is a 16 x 16 two’s complement multiplier that takes two 16-bit numbers and multiplies them together to form a 32-bit number. Four clockjnputs CPI - CP4 and four enable_inputs (EN1 - EN4)


    OCR Scan     		PDF CFB2402A CFB2402A 16-bit 32-bit CFBZ402A

    Untitled

    Abstract: No abstract text available
    Text: SGS-THOMSON ST10R 165 iM ig ia o iiU K g T r M n 16-BIT ROMLESS MICROCONTROLLER PRELIMINARY DATA High performance 16-bit CPU with 4-stage pipeline 100 nsinstruction cycle timeat20-MHz CPU clock 500 ns multiplication 16 x 16 bits , 1 jos division (32/16 bit)


    OCR Scan     		PDF ST10R 16-BIT timeat20-MHz 0071G02

    API3

    Abstract: No abstract text available
    Text: CFB2401B CFB2401B MPY - 1PL GENERAL DESCRIPTION: 16 X 16 TWO’S COMP PLAIN MPY, 1-STAGE PIPELINE CFB2401B is a 16 x 16 two’s complement multiplier that takes two 16-bit numbers and multiplies them together to form a 32-bit number. There is only one clock input CP to control the pipelining function.


    OCR Scan     		PDF CFB2401B CFB2401B 16-bit 32-bit API3

    Untitled

    Abstract: No abstract text available
    Text: LPR520 4 x 16-bit Multilevel Pipeline Register FEATURES DESCRIPTION □ Four 16-bit Registers The LPR520 is functionally compatible with the L29C520 but have 16-bit inputs and outputs. The LPR520 is implemented in low power CMOS. □ Implements Double 2-Stage Pipe­


    OCR Scan     		PDF LPR520 16-bit LPR520 L29C520 MIL-STD-883, 40-pin

    Untitled

    Abstract: No abstract text available
    Text: Æ 7 SGS-THOMSON •>71. llD giœi!J iMraD(g§ ST10F167 16-BIT MCU WITH 128K BYTE FLASH MEMORY PRELIMINARY DATA • High PerformanceCPU ■ 16-bit CPU with 4 stage pipeline. ■ 100 ns instruction cycle time at 20MHz CPU Clock. ■ 500ns multiplication (16*16 bit ,


    OCR Scan     		PDF ST10F167 16-BIT 20MHz 500ns 16-channel 10-bit. 144-Pin

    Untitled

    Abstract: No abstract text available
    Text: / IT G S-1 H 0 M S0 N #. SIMOtg^lULKgìfMnigg_ ST10R163 16-BIT ROMLESS MICROCONTROLLER D ATASH EET • High performance 16-bit CPU with 4-stage pipeline ■ 80ns instruction cycle time at 25-MHz CPU clock ■ 400 ns multiplication 16 x 16 bits , 800 ns


    OCR Scan     		PDF ST10R163 16-BIT 25-MHz

    T71N

    Abstract: LT17 t71c ST10 ST10F167 017FFE st10 Bootstrap TS cc30, thomson
    Text: SGS-THOMSON su ST10F167 16-BIT MCU W ITH 128K BYTE FLASH M EM O RY P R E L IM IN A R Y DA TA High PerformanceCPU 16-bit CPU with 4 stage pipeline. 100 ns instruction cycle time a t20M H z CPU Clock. 500ns multiplication 16*16 bit , 1 ms division (32/16 bit).


    OCR Scan     		PDF ST1OF167 16-BIT 20MHz 500ns add28 ST10F167-Q6 PQFP144 T71N LT17 t71c ST10 ST10F167 017FFE st10 Bootstrap TS cc30, thomson