MS-026
Abstract: MT55L256L32P MT55L256L36P MT55L256V32P MT55L256V36P MT55L512L18P MT55L512V18P
Text: 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM 8Mb ZBT SRAM MT55L512L18P, MT55L512V18P, MT55L256L32P, MT55L256V32P, MT55L256L36P, MT55L256V36P 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • • • • • •
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MT55L512L18P,
MT55L512V18P,
MT55L256L32P,
MT55L256V32P,
MT55L256L36P,
MT55L256V36P
100-Pin
119-Pin
165-pin
MT55L512L18P
MS-026
MT55L256L32P
MT55L256L36P
MT55L256V32P
MT55L256V36P
MT55L512V18P
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MT55L256L18P1T-10A
Abstract: MS-026 MT55L128L32P1 MT55L128L36P1 MT55L128V32P1 MT55L128V36P1 MT55L256L18P1 MT55L256L18P1T-10 MT55L256V18P1 84 FBGA thermal
Text: PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 4Mb ZBT SRAM MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • •
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MT55L256L18P1,
MT55L256V18P1,
MT55L128L32P1,
MT55L128V32P1,
MT55L128L36P1,
MT55L128V36P1
August/7/00
119-pin
165-pin
MT55L256L18P1
MT55L256L18P1T-10A
MS-026
MT55L128L32P1
MT55L128L36P1
MT55L128V32P1
MT55L128V36P1
MT55L256L18P1T-10
MT55L256V18P1
84 FBGA thermal
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K7Q161852A
Abstract: K7Q161852A-FC10 K7Q161852A-FC13 K7Q161852A-FC16 K7Q163652A K7Q163652A-FC10 K7Q163652A-FC13 K7Q163652A-FC16
Text: K7Q163652A K7Q161852A 512Kx36 & 1Mx18 QDRTM b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. April, 30, 2001 Advance 0.1 1. Amendment 1 Page 3,4 PIN NAME DESCRIPTION W 4A) : from Read Control Pin to Write Control
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K7Q163652A
K7Q161852A
512Kx36
1Mx18
512Kx36-bit,
1Mx18-bit
K7Q161852A
K7Q161852A-FC10
K7Q161852A-FC13
K7Q161852A-FC16
K7Q163652A
K7Q163652A-FC10
K7Q163652A-FC13
K7Q163652A-FC16
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PDF
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MT58L64L36P
Abstract: MS-026 MT58L128L18P MT58L128V18P MT58L64L32P MT58L64V32P MT58L64V36P
Text: NOT RECOMENDED FOR NEW DESIGNS 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2Mb SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, SingleCycle Deselect FEATURES
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MT58L128L18P,
MT58L64L32P,
MT58L64L36P;
MT58L128V18P,
MT58L64V32P,
MT58L64V36P
June/21/00
x32/36
165-Pin
March/3/00
MT58L64L36P
MS-026
MT58L128L18P
MT58L128V18P
MT58L64L32P
MT58L64V32P
MT58L64V36P
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10D-11
Abstract: K7R160982B K7R160982B-FC16 K7R160982B-FC20 K7R161882B K7R161882B-FC16 K7R161882B-FC20 K7R163682B K7R163682B-FC16 K7R163682B-FC20
Text: K7R163682B K7R161882B K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002 Advance 0.1 1. Change the Boundary scan exit order.
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K7R163682B
K7R161882B
K7R160982B
512Kx36
1Mx18
512Kx36-bit,
1Mx18-bit,
10D-11
K7R160982B
K7R160982B-FC16
K7R160982B-FC20
K7R161882B
K7R161882B-FC16
K7R161882B-FC20
K7R163682B
K7R163682B-FC16
K7R163682B-FC20
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PDF
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K7Q161864B-FC16
Abstract: D0-35 K7Q161864B K7Q163664B K7Q163664B-FC16
Text: K7Q163664B K7Q161864B 512Kx36 & 1Mx18 QDRTM b4 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Jan. 27, 2004 Advance 1.0 1. Final spec release Mar. 18, 2004 Final Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
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K7Q163664B
K7Q161864B
512Kx36
1Mx18
512Kx36-bit,
1Mx18-bit
K7Q161864B-FC16
D0-35
K7Q161864B
K7Q163664B
K7Q163664B-FC16
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K7M643635M-Q
Abstract: No abstract text available
Text: K7N643631M K7N641831M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAM TM Document Title 2Mx36 & 4Mx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. Sep. 30. 2002 Advance 0.1 1. Delete the speed bins FT : 7.5ns, 8.5ns / PP : 200MHz
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K7N643631M
K7N641831M
2Mx36
4Mx18
4Mx18-Bit
200MHz)
K7N643635M
K7N643631M)
50REF
K7M643635M-Q
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PDF
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K7N161801A
Abstract: K7N163601A
Text: K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM TM Document Title 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Initial document. Add JTAG Scan Order Add x32 org and industrial temperature . Add 165FBGA package Speed bin merge.
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K7N163601A
K7N161801A
512Kx36
1Mx18
1Mx18-Bit
165FBGA
K7N1636
K7N161801A
K7N163601A
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D0-35
Abstract: K7J161882B K7J161882B-FC16 K7J161882B-FC20 K7J161882B-FC25 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25
Text: K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram Dec. 26, 2002 Preliminary
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K7J163682B
K7J161882B
512Kx36
1Mx18
512Kx36-bit,
1Mx18-bit
165FBGA
D0-35
K7J161882B
K7J161882B-FC16
K7J161882B-FC20
K7J161882B-FC25
K7J163682B
K7J163682B-FC16
K7J163682B-FC20
K7J163682B-FC25
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IS61LPD51236A
Abstract: IS61LPD102418A IS61VPD102418A IS61VPD51236A
Text: IS61VPD51236a IS61VPD102418a IS61lPD51236a IS61LPD102418a 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and
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IS61VPD51236a
IS61VPD102418a
IS61lPD51236a
IS61LPD102418a
1024K
100-Pin
165-pin
IS61LPD102418A
IS61VPD102418A
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PDF
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IS61LPD102418A
Abstract: IS61LPD51236A IS61VPD102418A IS61VPD51236A
Text: ISSI IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and
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IS61VPD51236A
IS61VPD102418A
IS61LPD51236A
IS61LPD102418A
1024K
100-Pin
165-pin
package30
PK13197LQ
5M-1982.
IS61LPD102418A
IS61VPD102418A
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HM66AQB18202
Abstract: HM66AQB18202BP-40 HM66AQB36102 HM66AQB36102BP-40 HM66AQB36102BP-50 HM66AQB36102BP-60 HM66AQB9402
Text: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
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D-85622
D-85619
HM66AQB18202
HM66AQB18202BP-40
HM66AQB36102
HM66AQB36102BP-40
HM66AQB36102BP-50
HM66AQB36102BP-60
HM66AQB9402
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IS61LPS102418A
Abstract: IS61LPS25672A IS61LPS51236A IS61VPS102418A IS61VPS25672A IS61VPS51236A IS61LPS51236A-200TQLI 1024Kx18
Text: IS61VPS25672A IS61LPS25672A IS61VPS51236A IS61LPS51236A IS61VPS102418A IS61LPS102418A ISSI 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write
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IS61VPS25672A
IS61LPS25672A
IS61VPS51236A
IS61LPS51236A
IS61VPS102418A
IS61LPS102418A
1024K
JEDE30
PK13197LQ
5M-1982.
IS61LPS102418A
IS61LPS25672A
IS61LPS51236A
IS61LPS51236A-200TQLI
1024Kx18
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GS8342Q36E-200
Abstract: GS8342Q36E-250 GS8342Q36E-300
Text: Preliminary GS8342Q08/09/18/36E-300/250/200/167 36Mb SigmaQuad-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package
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GS8342Q08/09/18/36E-300/250/200/167
165-Bump
165-bump,
in-165-Pin
GS8342Q08GE-200I
165-Pin
GS8342Q08GE-167I
GS8342x36E-200T.
GS8342Q36E-200
GS8342Q36E-250
GS8342Q36E-300
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NC-2H
Abstract: K7B161825A K7B163225A K7B163625A
Text: K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Document Title 512Kx36/x32 & 1Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History 1. Initial draft 1. Add JTAG Scan Order 1. Add x32 org and industrial temperature .
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K7B163625A
K7B163225A
K7B161825A
512Kx36/32
1Mx18
512Kx36/x32
1Mx18-Bit
165FBGA
NC-2H
K7B161825A
K7B163225A
K7B163625A
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PDF
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K7N161801A
Abstract: K7N163201A K7N163601A
Text: K7N163601A K7N163201A K7N161801A Preliminary 512Kx36/32 & 1Mx18 Pipelined NtRAMTM Document Title 512Kx36/32 & 1Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 Draft Date History 1. Initial document. 1. Add JTAG Scan Order 1. Add x32 org and industrial temperature .
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K7N163601A
K7N163201A
K7N161801A
512Kx36/32
1Mx18
1Mx18-Bit
165FBGA
K7N1636
K7N161801A
K7N163201A
K7N163601A
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Untitled
Abstract: No abstract text available
Text: K7I163684B K7I161884B 512Kx36 & 1Mx18 DDRII CIO b4 SRAM 18Mb DDRII SRAM Specification 165FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
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K7I163684B
K7I161884B
512Kx36
1Mx18
165FBGA
11x15
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PDF
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Untitled
Abstract: No abstract text available
Text: 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM 8Mb SYNCBURST SRAM MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through FEATURES • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply VDD
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MT58L512L18F,
MT58L256L32F,
MT58L256L36F;
MT58L512V18F,
MT58L256V32F,
MT58L256V36F
July/18/00
119-Pin
165-pin
June/13/00
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation
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MT54V512H18E
512Kx18)
MT54V512H18E
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Untitled
Abstract: No abstract text available
Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE
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MT54V512H18A
165-Pin
MT54V512H18A
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IS61LPD51218A
Abstract: IS61LPD25636A IS61VPD25636A IS61VPD51218A
Text: ISSI IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and
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IS61VPD25636A
IS61LPD25636A
IS61VPD51218A
IS61LPD51218A
100-Pin
119-pin
165-pin
PK13197LQ
5M-1982.
IS61LPD51218A
IS61LPD25636A
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qfn 3x3 tray dimension
Abstract: XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga
Text: Device Package User Guide [Guide Subtitle] [optional] UG112 v3.5 November 6, 2009 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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UG112
UG072,
UG075,
XAPP427,
qfn 3x3 tray dimension
XCDAISY
BFG95
XC5VLX330T-1FF1738I
pcb footprint FS48, and FSG48
WS609
jedec so8 Wire bond gap
XC3S400AN-4FG400I
FFG676
XC4VLX25 cmos 668 fcbga
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IS61LPS25632A
Abstract: IS61LPS25636A IS61LPS51218A IS61VPS25636A IS61VPS51218A
Text: IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write
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IS61LPS51218A,
IS61LPS25636A,
IS61LPS25632A,
IS64LPS25636A,
IS61VPS51218A,
IS61VPS25636A
PK13197LQ
5M-1982.
IS61LPS25632A
IS61LPS25636A
IS61LPS51218A
IS61VPS25636A
IS61VPS51218A
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PDF
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Untitled
Abstract: No abstract text available
Text: K7N163645A K7N163245A K7N161845A 512Kx36/32 & 1Mx18 Pipelined NtRAMTM Document Title 512Kx36/32 & 1Mx18-Bit Pipelined NtRAM TM Revision History History Draft Date Remark 1. Initial document. 1. Add JTAG Scan Order 1. Add x32 org and industrial temperature .
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K7N163645A
K7N163245A
K7N161845A
512Kx36/32
1Mx18
1Mx18-Bit
165FBGA
K7N1636
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PDF
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