278MH Search Results

278MH Result Highlights (1)

Part	ECAD Model	Manufacturer	Description	Download	Buy
ADS1278MHFQ-MLS		Texas Instruments	Radiation Hardened 24-Bit 8-Ch Simultaneous-Sampling Delta-Sigma ADC 84-CFP -55 to 125

278MH Price and Stock

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MF Electronics Corp M1200-7.3278MHZ
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	M1200-7.3278MHZ		25			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments ADS1278MHFQ-MLS ADC, DELTA-SIGMA; Temperature Grade: MILITARY; Terminal Form: FLAT; No. of Terminals: 84; Package Code: QFF; Package Shape: SQUARE;
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	ADS1278MHFQ-MLS		452			1 - 10 - 100 - 1000 - 10000 -	Get Quote

278MH Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: 8201, 8202, 8203, 8204 Acceleration Processor Data Sheet Exar Confidential DS-0157-05 April 16, 2012, Exar , Inc. All rights reserved. 04/12 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Exar Corporation.	Original	DS-0157-05 8201I	PDF
CY7C1411BV18 Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18 Text: CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit CY7C1411BV18 CY7C1413BV18 CY7C1411BV18 CY7C1413BV18 CY7C1415BV18 CY7C1426BV18	PDF
CY7C1422AV18 Abstract: CY7C1423AV18 CY7C1424AV18 CY7C1429AV18 Text: CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit CY7C1422AV18 CY7C1423AV18 CY7C1424AV18 CY7C1429AV18	PDF
05564 Abstract: CY7C1522V18 CY7C1523V18 CY7C1524V18 CY7C1529V18 Text: CY7C1522V18, CY7C1529V18 CY7C1523V18, CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	CY7C1522V18, CY7C1529V18 CY7C1523V18, CY7C1524V18 72-Mbit 05564 CY7C1522V18 CY7C1523V18 CY7C1524V18 CY7C1529V18	PDF
CY7C1520V18-200BZXC Abstract: CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18 Text: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit CY7C1520V18-200BZXC CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18	PDF
CY7C1311BV18 Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18 36-Mbit 300-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 300-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1522V18 CY7C1529V18 CY7C1523V18 CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1522V18 CY7C1529V18 CY7C1523V18 CY7C1524V18 72-Mbit 300-MHz 278-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled	Original	CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 18-Mbit 300-MHz 600MHz)	PDF
CY7C1428AV18-250BZC Abstract: No abstract text available Text: CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 36-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency	Original	CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 36-Mbit 300-MHz CY7C1428AV18-250BZC	PDF
CY7C1522AV18 Abstract: CY7C1523AV18 CY7C1529AV18 Text: CY7C1522AV18 CY7C1529AV18 CY7C1523AV18 CY7C1524AV18 PRELIMINARY 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1522AV18 CY7C1529AV18 CY7C1523AV18 CY7C1524AV18 72-Mbit 300-MHz 18/CY7C1529AV18/CY7C1523AV18/CY7C1524AV18 CY7C1522AV18 CY7C1523AV18 CY7C1529AV18	PDF
CY7C1416BV18 Abstract: CY7C1418BV18 CY7C1420BV18 CY7C1427BV18 Text: CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 36-Mbit 300-MHz enab1416BV18 CY7C1416BV18 CY7C1418BV18 CY7C1420BV18 CY7C1427BV18	PDF

CY7C1511AV18 Abstract: CY7C1513AV18 CY7C1515AV18 CY7C1526AV18 Text: CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 72-Mbit CY7C1511AV18 CY7C1513AV18 CY7C1511AV18 CY7C1513AV18 CY7C1515AV18 CY7C1526AV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description • 36 Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces 	Original	CY7C1418AV18 CY7C1420AV18 CY7C1418AV18, CY7C1420AV18 CY7C1420AV18,	PDF
Untitled Abstract: No abstract text available Text: CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M × 9, 2M × 18, 1M × 36 ■ 300 MHz clock for high bandwidth	Original	CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit CY7C1429AV18, CY7C1424AV18	PDF
CY7C1517V18 Abstract: CY7C1519V18 CY7C1521V18 CY7C1528V18 Text: CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency	Original	CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit 300-MHz CY7C1517V18 CY7C1519V18 CY7C1521V18 CY7C1528V18	PDF
CY7C1522V18 Abstract: CY7C1523V18 CY7C1524V18 CY7C1529V18 Text: CY7C1522V18 CY7C1529V18 CY7C1523V18 CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 The CY7C1522V18, CY7C1529V18, CY7C1523V18, CY7C1524V18 are 1.8V Synchronous Pipelined SRAMs	Original	CY7C1522V18 CY7C1529V18 CY7C1523V18 CY7C1524V18 72-Mbit CY7C1522V18, CY7C1529V18, CY7C1523V18, CY7C1524V18 CY7C1522V18 CY7C1523V18 CY7C1529V18	PDF
Untitled Abstract: No abstract text available Text: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit CY7C1911BV18, CY7C1315BV18	PDF
CY7C1311BV18 Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18	PDF
M/288M- Abstract: No abstract text available Text: CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit QDR - II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 300-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency	Original	CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit 300-MHz Selects278-MHz M/288M-	PDF
Untitled Abstract: No abstract text available Text: CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 36-Mbit 300-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz 600MHz) SelecCY7C1911BV18 278-MHz	PDF

278MH Search Results

278MH Result Highlights (1)

278MH Price and Stock

MF Electronics Corp M1200-7.3278MHZ

Texas Instruments ADS1278MHFQ-MLS

278MH Datasheets Context Search

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CY7C1411BV18

CY7C1422AV18

05564

CY7C1520V18-200BZXC

CY7C1311BV18

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CY7C1428AV18-250BZC

CY7C1522AV18

CY7C1416BV18

CY7C1511AV18

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CY7C1517V18

CY7C1522V18

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CY7C1311BV18

M/288M-

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