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    2MX18 Search Results

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    2MX18 Price and Stock

    Rochester Electronics LLC NCP152MX180150TCG

    IC REG LIN 1.5V/1.8V 150MA 6XDFN
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    DigiKey NCP152MX180150TCG Bulk 102,000 1,043
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    Rochester Electronics LLC NCP152MX180280TCG

    IC REG LIN 1.8V/2.8V 150MA 6XDFN
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    DigiKey NCP152MX180280TCG Bulk 91,500 1,043
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    onsemi NCV8152MX180280TCG

    IC REG LINEAR 1.8V/2.8V 6XDFN
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    DigiKey NCV8152MX180280TCG Digi-Reel 39,548 1
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    NCV8152MX180280TCG Cut Tape 39,548 1
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    NCV8152MX180280TCG Reel 35,000 5,000
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    Avnet Americas NCV8152MX180280TCG Reel 15 Weeks 15,000
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    Mouser Electronics NCV8152MX180280TCG 5,000
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    Newark NCV8152MX180280TCG Reel 5,000
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    Avnet Asia NCV8152MX180280TCG 15 Weeks 5,000
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    Avnet Silica NCV8152MX180280TCG 16 Weeks 5,000
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    EBV Elektronik NCV8152MX180280TCG 17 Weeks 5,000
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    onsemi NCP702MX18TCG

    IC REG LINEAR 1.8V 200MA 6XDFN
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    DigiKey NCP702MX18TCG Digi-Reel 113 1
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    NCP702MX18TCG Cut Tape 113 1
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    NCP702MX18TCG Reel
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    RS NCP702MX18TCG Bulk 1
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    Rochester Electronics NCP702MX18TCG 51,000 1
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    Flip Electronics NCP702MX18TCG 2,029
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    onsemi NCV8702MX18TCG

    IC REG LINEAR 1.8V 200MA 6XDFN
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    DigiKey NCV8702MX18TCG Reel 3,000
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    Bristol Electronics NCV8702MX18TCG 2,980
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    Rochester Electronics NCV8702MX18TCG 1
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    Find more 2MX18 price and stock on Findchips.com

    2MX18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    K7A323600M

    Abstract: K7B321825M-QC65 K7A321800M
    Text: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary


    Original     		PDF K7A323600M K7A321800M 1Mx36 2Mx18 2Mx18-Bit 165FBGA K7A3236 165FBGA K7A323600M K7B321825M-QC65 K7A321800M

    K7M321825M

    Abstract: K7M321825M-QC75 K7M323625M K7M323625M-QC75
    Text: K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary


    Original     		PDF K7M323625M K7M321825M 1Mx36 2Mx18 2Mx18-Bit 165FBGA 165FBGA x18/x36 K7M321825M K7M321825M-QC75 K7M323625M K7M323625M-QC75

    K7M321825M

    Abstract: K7M323625M
    Text: K7M323625M K7M321825M Preliminary 1Mx36 & 2Mx18 Flow-Through NtRAM TM 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM FEATURES GENERAL DESCRIPTION • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O


    Original     		PDF K7M323625M K7M321825M 1Mx36 2Mx18 2Mx18-Bit 65V/-0 100-TQFP-1420A /119BGA K7M321825M K7M323625M

    Untitled

    Abstract: No abstract text available
    Text: K7P323674C K7P321874C 1Mx36 & 2Mx18 SRAM 36Mb Late Write SRAM Specification 119BGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,


    Original     		PDF K7P323674C K7P321874C 1Mx36 2Mx18 119BGA

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: K7Q323684M K7Q321884M 1Mx36 & 2Mx18 Preliminary b4 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. September 5, 2001 Advance 0.1 1. Changed Pin configuration at x36 organization.


    Original     		PDF K7Q323684M K7Q321884M 1Mx36 2Mx18 1Mx36-bit, 2Mx18-bit K7Q3236

    Untitled

    Abstract: No abstract text available
    Text: K7Q323682M K7Q321882M 1Mx36 & 2Mx18 Preliminary b2 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. September, 5 2001 Advance 0.1 1. Changed Pin configuration at x36 organization.


    Original     		PDF K7Q323682M K7Q321882M 1Mx36 2Mx18 1Mx36-bit, 2Mx18-bit

    Untitled

    Abstract: No abstract text available
    Text: K7R323684C K7R321884C K7R320984C Preliminary TM 1Mx36, 2Mx18 & 4Mx9 QDR II b4 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.


    Original     		PDF K7R323684C K7R321884C K7R320984C 1Mx36, 2Mx18

    Untitled

    Abstract: No abstract text available
    Text: K7R323682M K7R321882M K7R320982M K7R320882M 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001 Advance 0.1


    Original     		PDF K7R323682M K7R321882M K7R320982M K7R320882M 1Mx36 2Mx18 1Mx36-bit, 2Mx18-bit,

    Untitled

    Abstract: No abstract text available
    Text: K7B323625M K7B321825M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 History 1. Initial draft Draft Date May. 10. 2001 Remark Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary


    Original     		PDF K7B323625M K7B321825M 1Mx36 2Mx18 2Mx18-Bit 165FBGA x18/x36

    Untitled

    Abstract: No abstract text available
    Text: K7Q323652M K7Q321852M 1Mx36 & 2Mx18 Preliminary b2 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Sep. 5. 2001 Advance 0.1 1. Reserved pin for high density name change from NC to Vss/SA


    Original     		PDF K7Q323652M K7Q321852M 1Mx36-bit, 2Mx18-bit 1Mx36 2Mx18 -20part

    Untitled

    Abstract: No abstract text available
    Text: K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 History Draft Date Remark 1. Initial document. 1. Add 165FBGA package 1. Update JTAG scan order 2. Speed bin merge.


    Original     		PDF K7N323601M K7N321801M 1Mx36 2Mx18-Bit 2Mx18 165FBGA K7N3236

    Untitled

    Abstract: No abstract text available
    Text: K7I323684C K7I321884C Preliminary 1Mx36 & 2Mx18 DDRII CIO b4 SRAM 36Mb DDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,


    Original     		PDF K7I323684C K7I321884C 1Mx36 2Mx18 11x15

    Untitled

    Abstract: No abstract text available
    Text: K7Q323654M K7Q321854M 1Mx36 & 2Mx18 Preliminary b4 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Sep. 5, 2001 Advance 0.1 1. Reserved pin for high density name change from NC to Vss/SA


    Original     		PDF K7Q323654M K7Q321854M 1Mx36-bit, 2Mx18-bit 1Mx36 2Mx18 -20part

    SRAM 8T

    Abstract: No abstract text available
    Text: Preliminary K7D323674C K7D321874C 1Mx36 & 2Mx18 SRAM 36Mb DDR SRAM Specification 153BGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,


    Original     		PDF K7D323674C K7D321874C 1Mx36 2Mx18 153BGA 012MAX SRAM 8T

    K7R323682M-FC20

    Abstract: K7R320982M-FC20
    Text: K7R323682M K7R321882M K7R320982M K7R320882M Preliminary 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001


    Original     		PDF K7R323682M K7R321882M K7R320982M K7R320882M 1Mx36 2Mx18 1Mx36-bit, 2Mx18-bit, K7R323682M-FC20 K7R320982M-FC20

    Untitled

    Abstract: No abstract text available
    Text: IS61QDPB42M18A/A1/A2 IS61QDPB41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES • • • • • • • • • • • • • • • • • • • • • 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data


    Original     		PDF IS61QDPB42M18A/A1/A2 IS61QDPB41M36A/A1/A2 2Mx18, 1Mx36 2Mx18 QV13x15 13x15

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B42M18A/A1/A2 IS61DDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP Burst 4 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     1Mx36 and 2Mx18 configuration available.


    Original     		PDF IS61DDP2B42M18A/A1/A2 IS61DDP2B41M36A/A1/A2 2Mx18, 1Mx36 2Mx18 13x15

    IS61DDB21M36A

    Abstract: No abstract text available
    Text: IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II Burst 2 CIO SYNCHRONOUS SRAM FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 1Mx36 2Mx18 13x15

    D0-35

    Abstract: No abstract text available
    Text: User Guide for QDRII as QDRI 36Mb QDRI 4Busrt B-die Advance 1Mx36 & 2Mx18 QDR TM b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit QDR TM SRAM Technical Note Revision History Rev. No. 0.0 History Draft Date Remark 1. Initial document. June. 19, 2003 Advance The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the


    Original     		PDF 1Mx36 2Mx18 1Mx36-bit, 2Mx18-bit 11x15 D0-35

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data


    Original     		PDF IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 1Mx36 2Mx18 ecIS61QDP2B41M36A-400B4LI IS61QDP2B42M18A-400B4I IS61QDP2B42M18A-400B4LI IS61QDP2B41M36A-333B4I

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B22M18A/A1/A2 IS61DDP2B21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     1Mx36 and 2Mx18 configuration available.


    Original     		PDF IS61DDP2B22M18A/A1/A2 IS61DDP2B21M36A/A1/A2 2Mx18, 1Mx36 1Mx36 2Mx18 13x15

    Untitled

    Abstract: No abstract text available
    Text: IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II Burst 2 CIO SYNCHRONOUS SRAM FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 1Mx36 2Mx18 IS61DDB21M36A-333B4I IS61DDB21M36A-333B4LI IS61DDB22M18A-333B4I IS61DDB22M18A-333B4LI

    Untitled

    Abstract: No abstract text available
    Text: IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 2 Synchronous SRAM JANUARY 2013 (2.5 CYCLE READ LATENCY) FEATURES •                     1Mx36 and 2Mx18 configuration available.


    Original     		PDF IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 1Mx36 2Mx18 IS61QDPB21M36A-333B4I IS61QDPB21M36A-333B4LI IS61QDPB22M18A-333B4I IS61QDPB22M18A-333B4LI