K7A323600M

Abstract: K7B321825M-QC65 K7A321800M
Contextual Info: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

K7M321825M

Abstract: K7M321825M-QC75 K7M323625M K7M323625M-QC75
Contextual Info: K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

K7M321825M

Abstract: K7M323625M
Contextual Info: K7M323625M K7M321825M Preliminary 1Mx36 & 2Mx18 Flow-Through NtRAM TM 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM FEATURES GENERAL DESCRIPTION • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O

Contextual Info: K7P323674C K7P321874C 1Mx36 & 2Mx18 SRAM 36Mb Late Write SRAM Specification 119BGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: K7Q323684M K7Q321884M 1Mx36 & 2Mx18 Preliminary b4 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. September 5, 2001 Advance 0.1 1. Changed Pin configuration at x36 organization.

Contextual Info: K7Q323682M K7Q321882M 1Mx36 & 2Mx18 Preliminary b2 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. September, 5 2001 Advance 0.1 1. Changed Pin configuration at x36 organization.

Contextual Info: K7R323684C K7R321884C K7R320984C Preliminary TM 1Mx36, 2Mx18 & 4Mx9 QDR II b4 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

Contextual Info: K7R323682M K7R321882M K7R320982M K7R320882M 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001 Advance 0.1

Contextual Info: K7B323625M K7B321825M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 History 1. Initial draft Draft Date May. 10. 2001 Remark Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

Contextual Info: K7Q323652M K7Q321852M 1Mx36 & 2Mx18 Preliminary b2 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Sep. 5. 2001 Advance 0.1 1. Reserved pin for high density name change from NC to Vss/SA

Contextual Info: K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 History Draft Date Remark 1. Initial document. 1. Add 165FBGA package 1. Update JTAG scan order 2. Speed bin merge.

Contextual Info: K7I323684C K7I321884C Preliminary 1Mx36 & 2Mx18 DDRII CIO b4 SRAM 36Mb DDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

Contextual Info: K7Q323654M K7Q321854M 1Mx36 & 2Mx18 Preliminary b4 SRAM QDRTM Document Title 1Mx36-bit, 2Mx18-bit QDRTM SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Sep. 5, 2001 Advance 0.1 1. Reserved pin for high density name change from NC to Vss/SA

SRAM 8T

Contextual Info: Preliminary K7D323674C K7D321874C 1Mx36 & 2Mx18 SRAM 36Mb DDR SRAM Specification 153BGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

K7R323682M-FC20

Abstract: K7R320982M-FC20
Contextual Info: K7R323682M K7R321882M K7R320982M K7R320882M Preliminary 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001

Contextual Info: IS61QDPB42M18A/A1/A2 IS61QDPB41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES • • • • • • • • • • • • • • • • • • • • • 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data

Contextual Info: IS61DDP2B42M18A/A1/A2 IS61DDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP Burst 4 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     1Mx36 and 2Mx18 configuration available.

IS61DDB21M36A

Contextual Info: IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II Burst 2 CIO SYNCHRONOUS SRAM FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

D0-35

Contextual Info: User Guide for QDRII as QDRI 36Mb QDRI 4Busrt B-die Advance 1Mx36 & 2Mx18 QDR TM b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit QDR TM SRAM Technical Note Revision History Rev. No. 0.0 History Draft Date Remark 1. Initial document. June. 19, 2003 Advance The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

Contextual Info: IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data

Contextual Info: IS61DDP2B22M18A/A1/A2 IS61DDP2B21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     1Mx36 and 2Mx18 configuration available.

Contextual Info: IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II Burst 2 CIO SYNCHRONOUS SRAM FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP Burst 2 Synchronous SRAM JANUARY 2013 (2.5 CYCLE READ LATENCY) FEATURES •                     1Mx36 and 2Mx18 configuration available.