32 MHZ Search Results

OSD19

Abstract: CCTV DISTRIBUTION NETWORK diagram CCTV DISTRIBUTION NETWORK single line diagram OSD13 OSD23 ADV3200 ADV3201 D0717 ADV3201ASWZ KVM SWITCH schematic
Contextual Info: 300 MHz, 32 x 32 Buffered Analog Crosspoint Switch ADV3200/ADV3201 FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VPOS VNEG DVCC DGND CLK 193-BIT SHIFT REGISTER DATA OUT DATA IN 193 UPDATE CS RESET PARALLEL LATCH 192 SYNC-TIP CLAMP . . . . 32 32 × 5:32

Contextual Info: 300 MHz, 32 x 32 Buffered Analog Crosspoint Switch ADV3200/ADV3201 FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS VPOS VNEG DVCC DGND CLK 193-BIT SHIFT REGISTER DATA OUT DATA IN 193 UPDATE CS RESET PARALLEL LATCH 192 SYNC-TIP CLAMP . . . . 32 32 × 5:32

tmp68301af

Abstract: TMP68301 LS 2025 TMP68303 MC68230 TMP68450 MC66681 QFP-100 TMP68230 TLCS-68000
Contextual Info: 16/32-bit Microprocessor & Peripheral LS I TLCS-68000 Family X44 Frequency MHZ Function Typ« No. 16-bit MPU (internal 32-bit. external 16-bit) TMP68000 CMOS 16-bit MPU TMP68HC000 16-bit virtual memory MPU TMP68010 32-bit MPU (internal 32-bit, external 32-bit)

intel 80387sx

Abstract: 80376 80387SX cmps a13 BLD386 intel 82370 80386 240182 architecture of microprocessor 80386 Multitasking of microprocessor 80386 intel
Contextual Info: 376 TM HIGH PERFORMANCE 32-BIT EMBEDDED PROCESSOR Y Full 32-Bit Internal Architecture 8- 16- 32-Bit Data Types 8 General Purpose 32-Bit Registers Extensive 32-Bit Instruction Set Y High Performance 16-Bit Data Bus 16 or 20 MHz CPU Clock Two-Clock Bus Cycles

LM3S3748-IQC50-A0T datasheet

Abstract: LM3S3748 PWM generator by using microcontroller cortex m3 pwm Generator SPI pwm generator stellaris usb flash drive LM3S3748-IQC50-A0 Quadrature Encoder
Contextual Info: LM3S3748 Microcontroller • Up to a maximum of 32 configurable DMA channels, 32 JTAG 128 KB Flash NVIC ARM Cortex -M3 SWD 50 MHz 32 32 ROM ■ Clocks, Reset System Control Systick Timer 2 SSI/SPI 4 Timer/PWM/CC P Each 32-bit or 2x16-bit Watchdog Timer

Contextual Info: MEMORIES FIFO M emories ★Under developm ent Type Capacity Configuration Operating frequency MHz MAX. Model No. 25 —i 35 Access time(ns) 15 20 25 35 Package SKDIP QFJ 28 28 28 28 28 28 32 — 28 28 32 28 32 28 32 28 32 50 DIP LH5481 LH5491 j — LH5496

B12 GDM

Abstract: AD8117 AD8117ABPZ AD8118 a14 gdm OP30 AD8117-EVAL
Contextual Info: 500 MHz, 32 x 32 Buffered Video Crosspoint Switch AD8117/AD8118 Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM FEATURES Large, 32 x 32 High Speed, Nonblocking Switch Array G = 1 AD8117 or G = 2 (AD8118) Operation Differential or Single-Ended Operation

80960HA-25

Abstract: 80960Cx ct 9372 electronics and communication engineering project Non-Pipelined processor 0X00 80960HA 80960HD 80960HT 272495
Contextual Info: A ADVANCE INFORMATION 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers — 1.2 Gbyte Internal Bandwidth 75 MHz

LM3S5749

Abstract: pwm Generator temperature controller using microcontroller LM3S3748 PWM generator by using microcontroller
Contextual Info: LM3S5749 Microcontroller • Up to a maximum of 32 configurable DMA channels, 32 JTAG 256 KB Flash NVIC ARM Cortex -M3 SWD 80 MHz ■ 32 96 KB SRAM 32 3 UARTs ■ ROM Clocks, Reset System Control ■ ■ ■ 2 SSI/SPI 4 Timer/PWM/CC P Each 32-bit or 2x16-bit

stellaris

Abstract: TTCAN LM3S3748 LM3S5000
Contextual Info: LM3S5632 Microcontroller • Up to a maximum of 32 configurable DMA channels, 32 JTAG 256 KB Flash NVIC ARM Cortex -M3 SWD 80 MHz ■ 32 96 KB SRAM 32 3 UARTs ■ ROM Clocks, Reset System Control ■ ■ ■ 2 SSI/SPI 4 Timer/PWM/CC P Each 32-bit or 2x16-bit

intel CORE i3 instruction set

Abstract: 27249 A312H FAIU
Contextual Info: ADVANCE INFORMATION intei 80960H A /H D /H T 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers — 1.2 Gbyte Internal Bandwidth 75 MHz

D401A

Abstract: D401a datasheet D405 NR pp d115 PIC18CXXX ssp i2c d401b D403 A D403 transistor datasheet d405
Contextual Info: Section 32. Electrical Specifications HIGHLIGHTS Introduction . 32-2 Absolute Maximums. 32-3

27248

Abstract: 80960HT
Contextual Info: ADVANCE INFORMATION in te i 80960H A/H D/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • ■ ■ 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Blt Global Registers — Sixteen 32-Bit Local Registers — 1.2 Gbyte Internal Bandwidth 75 MHz

ADV3202

Abstract: ADV3203 OSD13 MS-026-BGA-HD
Contextual Info: 300 MHz, 32 x 16 Buffered Analog Crosspoint Switch ADV3202/ADV3203 FEATURES Large, 32 × 16, nonblocking switch array G = +1 ADV3202 or G = +2 (ADV3203) operation 32 × 32 pin-compatible version available (ADV3200/ADV3201) Single +5 V, dual ±2.5 V, or dual ±3.3 V supply (G = +2)

oasis

Abstract: S2025 DIN20P
Contextual Info: DEVICE SPECIFICATION 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH FEATURES • • • • • • • • GENERAL DESCRIPTION 32 x 32 differential crosspoint switch Full broadcast switching capability

Contextual Info: LSI LOGIC L64032 32 x 32-Bit Multiplier-Accumulator Description The L64032 is a high-speed 32 x 32-bit parallel multiplier-accumulator which provides single precision 32 x 32 and multiple precision (64 x 64) fixed point multiplication and single preci­

uk ah 102 m capacitor

Abstract: DFP 830 uk ah 102 m capacitor
Contextual Info: Features * Fast Read Access Tim e - 90 ns * Low Power CMOS Operation - 100 |jA max. Standby - 40 mA max. Active at 5 MHz * JEDEC Standard Packages - 32 Lead PLCC - 32-Lead 600-mii PDIP and Cerdip - 32-Lead 450-mil SOIC SOP - 32-Lead TSOP * 5 V + 10% Supply

Contextual Info: Features * Fast Read Access Time - 70 ns * Low Power CMOS Operation - 100 |jA max. Standby - 30 mA max. Active at 5 MHz * JEDEC Standard Packages - 32-Lead 600-mii PDIP - 32-Lead 450-mil SOIC SOP - 32-Lead PLCC - 32-Lead TSOP * 5V + 10% Supply * High Reliability CMOS Technology

Crossbow

Abstract: S 187 S2024B-6 register file DIN31
Contextual Info: DEVICE SPECIFICATION “CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH “CROSSBOW” X 32 800 MBIT/S CROSSPOINT SWITCH BiCMOS PECL 32 CLOCK GENERATOR FEATURES GENERAL DESCRIPTION • Full broadcast switching capability • 32 x 32 crosspoint structure, expandable to 64 x

S08SCIV1

Abstract: 9s08r freescale superflash
Contextual Info: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 Data Sheet HCS08 Microcontrollers MC9S08RG60/D Rev. 1.11 06/2005 freescale.com MC9S08RG60 Data Sheet Covers: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 MC9S08RG60/D

freescale superflash

Abstract: HCS08 ADC code example assembly
Contextual Info: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 Data Sheet HCS08 Microcontrollers MC9S08RG60/D Rev. 1.11 06/2005 freescale.com MC9S08RG60 Data Sheet Covers: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 MC9S08RG60/D

Contextual Info: SPA-100-32-003-SMA DATA SHEET 500 MHz to 10 GHz, Broadband Amplifier with 25 dBm, 32 dB Gain and SMA SPA-100-32-003-SMA is a broadband GaAs PHEMT MMIC-based 300 mW coaxial low noise amplifier, operating in the 0.5 to 10 GHz frequency range. The amplifier offers 32 dBm of P1dB and 32 dB small signal gain, with the excellent gain

ST20450X40S

Abstract: A2531 60F5 enhanced ST20 manual st20 ST20 TOOLSET ST20 manual ST20 Embedded Toolset Reference Manual ST20450 ST20C4
Contextual Info: ST20450  32 BIT MICROPROCESSOR ENGINEERING DATA FEATURES • Enhanced 32-bit CPU • 0 to 40 MHz processor clock • 32 MIPS at 40 MHz • fast integer/bit operations ■ System Services 32-bit Processor 16 Kbytes on-chip SRAM • 160 Mbytes/s maximum bandwidth

Contextual Info: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 Data Sheet HCS08 Microcontrollers MC9S08RG60/D Rev. 1.11 06/2005 freescale.com MC9S08RG60 Data Sheet Covers: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 MC9S08RG60/D