7824 MA datasheet
Abstract: No abstract text available
Text: TGF2023-2-05 25 Watt Discrete Power GaN on SiC HEMT Applications • Defense & Aerospace • Broadband Wireless Product Features • • • • • • • Functional Block Diagram Frequency Range: DC - 18 GHz 43 dBm Nominal PSAT at 3 GHz 78.3% Maximum PAE
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TGF2023-2-05
TQGaN25
TGF2023-2-05
DC-18
7824 MA datasheet
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REF028
Abstract: CLKB25 AD591 RSVD16 PC PSU CIRCUIT diagram ad54 ad5462 AD42/172Z-0 AD29 AD30
Text: B Layout and Circuit Diagrams This appendix contains layout and circuit details of the PCI backplane. 1 July 1997 – Subject To Change Layout and Circuit Diagrams B–1 zz001 Figure B–1 Backplane Arrangement in a PC/AT Chassis. B–2 Layout and Circuit Diagrams
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zz001
zz008
REF028
CLKB25
AD591
RSVD16
PC PSU CIRCUIT diagram
ad54
ad5462
AD42/172Z-0
AD29
AD30
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Untitled
Abstract: No abstract text available
Text: 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs AD9512-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM VS FUNCTION DSYNC DSYNCB SYNCB, RESETB PDB DETECT SYNC GND RSET VREF AD9512-EP PROGRAMMABLE DIVIDERS AND PHASE ADJUST SYNC STATUS
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AD9512-EP
CP-48-1)
AD9512UCPZ-EP
AD9512UCPZ-EP-R7
48-Lead
CP-48-1
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2128-80LQ
Abstract: No abstract text available
Text: ® ispLSI and pLSI 2128 High Density Programmable Logic Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay Output Routing Pool ORP — — — — — — — TTL Compatible Inputs and Outputs
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8-100LT
176-Pin
2128-80LQ
160-Pin
2128-80LM*
2128-100LM*
2128-80LQ
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AA13
Abstract: AA19 AC11 AC13 AD12
Text: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool
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212A/3320
3320-100LQ
208-Pin
3320-100LB320
320-Ball
3320-100LM*
3320-70LQ
3320-70LB320
AA13
AA19
AC11
AC13
AD12
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AA13
Abstract: AA19 AC11 AC13 AD12
Text: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool
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212A/3320
3320-100LQ
208-Pin
3320-100LB320
320-Ball
3320-70LQ
3320-70LB320
041A/3320
AA13
AA19
AC11
AC13
AD12
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AA13
Abstract: AA19 AC11 AC13 AD12
Text: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool
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212A/3320
3320-100LQ
208-Pin
3320-100LB320
320-Ball
3320-100LM*
3320-70LQ
3320-70LB320
AA13
AA19
AC11
AC13
AD12
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Untitled
Abstract: No abstract text available
Text: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5
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2128/A
0212/2128A
2128/A
128A-100LQ160
128A-100LT176
128A-80LQ160
128A-80LT176
2128-100LQ
2128-100LT
2128-80LQ
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ORP 112
Abstract: No abstract text available
Text: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5
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2128/A
128A-100LQ160
160-Pin
128A-100LT176
176-Pin
128A-80LQ160
128A-80LT176
2128-100LQ
ORP 112
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2128-80LQ
Abstract: No abstract text available
Text: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5
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2128/A
128A-100LQ160
160-Pin
128A-100LT176
176-Pin
128A-80LQ160
128A-80LT176
2128-100LQ
2128-80LQ
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Untitled
Abstract: No abstract text available
Text: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool
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320BGA/3320
212A/3320
3320-100LQ
3320-100LB320
3320-100LM*
3320-70LQ
3320-70LB320
3320-70LM*
208-Pin
320-Ball
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B272
Abstract: BC470
Text: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency
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0212B/3160
3160-125LQ
208-Pin
3160-125LB272
272-Ball
3160-100LQ
3160-100LB272
3160-70LQ
B272
BC470
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Untitled
Abstract: No abstract text available
Text: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency
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0212B/3160
3160-125LQ
3160-125LB272
3160-125LM*
3160-100LQ
3160-100LB272
3160-100LM*
3160-70LQ
3160-70LB272
3160-70LM*
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B272
Abstract: 203d6
Text: ispLSI 3160 High Density Programmable Logic Features Functional Block Diagram E3 E2 E1 E0 A0 ORP OR Array ORP A2 A3 D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay
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0212B/3160
3160-125LQ
208-Pin
3160-125LB272
272-Ball
3160-125LM*
3160-100LQ
3160-100LB272
B272
203d6
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203d6
Abstract: B272
Text: ispLSI 3160 Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay
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0212B/3160
3160-125LQ
208-Pin
3160-125LB272
272-Ball
3160-100LQ
3160-100LB272
3160-70LQ
203d6
B272
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B272
Abstract: No abstract text available
Text: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency
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0212B/3160
3160-125LQ
208-Pin
3160-125LB272
272-Ball
3160-125LM*
3160-100LQ
3160-100LB272
B272
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2128-80LT
Abstract: No abstract text available
Text: ® ispLSI and pLSI 2128 High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable
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STEL-2105
Abstract: 2105 LINEAR STEL-2110A STEL-2130A STEL-2130 2105 STEL-2100A receiver timing recovery discriminator integrat
Text: STEL-2105 Data Sheet STEL-2105 Digital Downconverter & Bit Synchronizer/QPSK Demodulator For Cable Applications R TABLE OF CONTENTS FEATURES AND BENEFITS . BLOCK DIAGRAM.
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STEL-2105
STEL-2105
2105 LINEAR
STEL-2110A
STEL-2130A
STEL-2130
2105
STEL-2100A
receiver timing recovery discriminator integrat
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E2633
Abstract: 2128A Si 21 C28E
Text: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay • IN-SYSTEM PROGRAMMABLE D0 C7 A1 C6 A2 A3 Logic Array A4 A5 D Q D Q D Q
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2128/A
No2128A-100LT176
176-Pin
128A-80LQ160
160-Pin
128A-80LT176
2128-100LQ
2128-100LT
E2633
2128A
Si 21
C28E
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74LS158PC
Abstract: 74S158PC Z1212 54LS158DM 54S158DM 74LS158DC 74LS158FC 74S158DC 74S158FC 74LS158D
Text: 1 NATIONAL SEdlCOND {LOGIC} DEE D | bS01122 DQb3fi47 ö | _ T-66-21-53 158 CONNECTION DIAGRAM PINOUT A 54S/74S158 54LS/74LS158 •E nr haE QUAD 2-INPUT MULTIPLEXER TÏ1 v c c ioa Ts] ë 2a [ I Í3 ]l,c lo b [s 2]ZC H ]lo c lod lib [ I
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bS01152
DQb30
T-66-21-53
54S/74S158
54LS/74LS158
74S158PC,
74LS158PC
74S158DC,
74LS158DC
54S158DM,
74LS158PC
74S158PC
Z1212
54LS158DM
54S158DM
74LS158FC
74S158DC
74S158FC
74LS158D
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Untitled
Abstract: No abstract text available
Text: 158 CO NNECTIO N DIAGRAM PINOUT A IS/74S158 6 / o !'J 54LS/74LS158 , / , v .J QUAD 2-INPUT MULTIPLEXER DESCRIPTION — T h e ’158 is a high speed quad 2-input m ultiplexer. It selects fo u r bits of data from tw o sources using the com m on Select and Enable
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IS/74S158
54LS/74LS158
54/74S
54/74LS
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37 PIN TFT MOBILE DISPLAY
Abstract: Single Chip Microcomputers Ultra mini CMOS camera transistor ck 112 mn1880 39 PIN TFT MOBILE DISPLAY MN194 MN1940
Text: Contents Type Number List 3 Application Block Diagrams . 21 Video Applications. 23 V C R System. ©TV-VCR Com bination.
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54ACT
Abstract: 74AC
Text: AC158 • ACT 158 54 AC/74 AC 158 • 54ACT/74ACT158 Quad 2-Input Multiplexer Description Connection Diagrams The ’AC/’ACT158 is a high-speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the
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ACT158
AC/74
54ACT/74ACT158
ACT158
54/74AC/ACT
54ACT
74AC
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Untitled
Abstract: No abstract text available
Text: AC158 • ACT158 54AC/74AC158 • 54ACT/74ACT 158 Quad 2-Input Multiplexer Connection Diagrams Description The ’AC/'ACT158 is a high-speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the
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AC158
ACT158
54AC/74AC158
54ACT/74ACT
54/74AC/ACT
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