LTC2314-14

Abstract: 7803 3V 1A positive voltage regulator 1407A1 l 7803 3V Positive Voltage Regulator LTC5551 LTC6947 LTM2987 LT6236 LTC5577
Contextual Info: May 2014 New Products Catalog High Performance Analog ICs LTC6947 Ultralow Noise and Spurious 0.35GHz to 6GHz Fractional-N Synthesizer LTM2987 16-Channel µModule PMBus Power System Manager LTC3128 3A Monolithic Buck-Boost Supercapacitor Charger and Balancer with Accurate Input Current Limit

R807D

Contextual Info: R8070 *» Rockwell R8070 T1/CEPT PCM Transceiver INTRODUCTION FEATURES The R ockw ell R 8070 T1/C EPT PCM Transceiver is a m onolithic silicon gate C M O S device designed to im ple m en t PCM tra n s­ m itter and receiver functions applied in primary-rate digital carrier

Contextual Info: Preliminary Data Sheet May 1997 microelectronics group Lucent Technologies Bell Labs Innovations T7698 QuadT1/E1 Line Interface and Octal T1/E1 Monitor Features • Fully integrated quad T1/E1 line transceiver and octal T1/E1 receive framer/monitor with HDLC pro­

Contextual Info: Preliminary Data Sheet May 1997 microelectronics group Lucent Technologies Bell Labs Innovations T7698 QuadT1/E1 Line Interface and Octal T1/E1 Monitor Features • Fully integrated quad T1/E1 line transceiver and octal T1/E1 receive framer/monitor with HDLC pro­

Contextual Info: Preliminary Data Sheet May 1998 microel ect ro nic s group Lucent Technologies Bell Labs Innovations T7698 QuadT1/E1 Line Interface and Octal T1/E1 Monitor Features • Fully integrated quadT1/E1 line interface and octal T1/E1 receive framer/monitor with HDLC proces­

Lucent SLC 2000

Abstract: f 4556 GR-253-CORE GR-499-CORE T7690 T7698 SA6H T7698-FL3-DB
Contextual Info: Data Sheet January 1999 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • ■ ■ ■ ■ Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities. Hardware and software reset options.

2795C

Abstract: Digital Alarm Clock by ttl dis 5261 b f 4556 GR-253-CORE GR-499-CORE T7690 T7698 lucent dacs ii
Contextual Info: Data Sheet May 2002 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • ■ ■ ■ ■ ■ ■ Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities. Hardware and software reset options.

dis 5261 b

Abstract: f 4556 la 4548 T7630 T7690 T7698 Z915
Contextual Info: Preliminary Data Sheet May 1997 microelectronics group Lucent Technologies Bell Labs Innovations T7698 QuadT1/E1 Line Interface and Octal T1/E1 Monitor Features • Fully integrated quad T1/E1 line transceiver and octal T1/E1 receive framer/monitor with HDLC pro­

Contextual Info: Data Sheet January 1999 microelectronics group Lucent Technologies Bell Labs Innovations T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities.

lucent dacs ii

Abstract: CRC-4 "Analog Line Interface" 7495 data sheet ANSI T1.102-93 dis 5261 b et 312 slc 500 circuit diagram T7698
Contextual Info: Advisory November 1998 T7698 Device Advisory for Version 2 of the Device Data Pattern Limitation of the LIU Internal Full Local Loopback FLLOOP Without Zero Substitution Coding One of the loopback modes in the quad line interface unit is the full local loopback (FLLOOP). This mode internally connects the LIU transmit driver to the LIU line receiver circuit. This loopback mode is controlled by primary (LIU) registers 6, 7, 8, and 9, bits 3 and 4; registers 6 through 9 control channels 1 through 4 of the

f 4556

Abstract: GR-253-CORE GR-499-CORE T7690 T7698 SR52 W 18
Contextual Info: Data Sheet September 2002 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities. ■ ■ ■ ■ Hardware and software reset options.

SR52 W 18

Abstract: GR-253-CORE GR-499-CORE PR11 T7690 T7698 uig823
Contextual Info: a e re 8 AdLib OCR Evaluation systems Data Sheet September 2002 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features . Integrated quad T1/E1 line interface and octal T1/ El receive frame monitor with HDLC processor provides system QoS capabilities .

TTK SG 2368

Abstract: BV EI 303 3628 7 segment LD 1106 BS LM 6863 D I8253 yx 8018 0308 082c ez 422 BV EI 304 3083 0429 01 2701 00 RELE 12,8 mhz e 4895 lf
Contextual Info: AP-55A APPLICATION NOTE i n t e i A u g u s t 1979 S.A. Distributor E l e c t r o n ic \ \ B u il d in g E l e m e n t s p t y l t d PURVEYORS OF a l l ELECTRONIC COMWNENTS Tel eph on e 7 8 - 9 2 2 1 / 6 P O B o x 4 6 0 9 , Pretoria T e l e x 3 01 8 1 S A

c8c1

Contextual Info: Im •■ § QT1F-P/us Device l/lf l T r T H ■ Quad T1 Framer-P/i/s TXC-03103 DATASHEET FEATURES DESCRIPTION • D4 SF; ESF (including HDLC Link support), and transparent framing modes • Delects, counts and forces line code errors (BPVs and excess zeros), CFC errors (ESF only), and frame bit

DMO 565 R

Abstract: chn 924 CHN G4 120
Contextual Info: xr XRT86L30 PRELIMINARY SINGLE T1/E1/J1 FRAMER/LIU COMBO JUNE 2005 REV. P1.0.2 GENERAL DESCRIPTION The XRT86L30 is a single channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

dmo 565 r

Abstract: 8214a CHN 549 chn 924 CHN 507 CHN 522 CHN 703 ST MEET CHN 507 chn 751 CHN 534
Contextual Info: XRT86L30 PRELIMINARY PRELIMINARY SINGLE T1/E1/J1 FRAMER/LIU COMBO MAY 2004 REV. P1.0.1 GENERAL DESCRIPTION The XRT86L30 is a single channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L30 provides protection

CHN 932

Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO APRIL 2004 REV. P1.1.0 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection

DMO 565 R

Abstract: chn 530 CHN 507 CHN 549 Transistor Checker Model LB-1 CHN 519 CHN 534 ST MEET CHN 507 CHN 545 chn 542
Contextual Info: XRT86L30 SINGLE T1/E1/J1 FRAMER/LIU COMBO JANUARY 2008 REV. 1.0.1 GENERAL DESCRIPTION The XRT86L30 is a single channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

dmo 565 r

Abstract: CHN 522 chn 542 chn 621 CHN 616 CHN 507 chn 638 chn 537 chn 543 CHN 618
Contextual Info: xr XRT86VL32 PRELIMINARY PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO SEPTEMBER 2004 REV. P1.0.1 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL32 provides protection

DMO 565 R

Abstract: chn 648 equivalent CHN 507 CHN 618 CHN 552 TS13 SCR PIN CONFIGURATION CHN 035 dmo 265 chn 605 nB00
Contextual Info: XRT86VL32 PRELIMINARY PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO APRIL 2004 REV. P1.0.0 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL32 provides protection

DMO 565 R

Abstract: CHN 652 CHN 933 chn 539 W0104 CHN 628 CHN 523 chn 648 equivalent 3667 ict XRT86L34IB
Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO MAY 2004 REV. P1.1.1 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection

dmo 565 r

Abstract: 8205A T1555 CHN G4 136 E1518 CHN 507 TR54016 XRT84V24 XRT86L30 XRT86L30IB
Contextual Info: XRT86L30 SINGLE T1/E1/J1 FRAMER/LIU COMBO MARCH 2007 REV. 1.0.0 GENERAL DESCRIPTION The XRT86L30 is a single channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

DMO 565 R

Abstract: chn 656 chn 637 chn 547 CHN 549 dmo 265 CHN 922 equivalent CHN 632 CHN 645 chn 648 equivalent
Contextual Info: XRT86L34 PRELIMINARY PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.3 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L34 provides protection

chn 542

Contextual Info: xr XRT86VL32 PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO FEBRUARY 2005 REV. P1.0.3 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .