Untitled
Abstract: No abstract text available
Text: S A M S U N G S E M I C O N D U C T O R INC 02 D E I 7Tt.4m2 DOUbHTb □ f D " 5 7 - - 2 V KS54HCTLS 4 A KS74HCTLS Hex Schmitt-Trigger Inverters FEATURES DESCRIPTION • Function, ptn-out, speed and drive compatibility with 54f74LS logic family • Low power consumption characteristic of CMOS
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KS54HCTLS
KS74HCTLS
54f74LS
7Tb414S
90-XO
14-Pin
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Untitled
Abstract: No abstract text available
Text: SAMSUNG S E M I CO ND UCTOR INC D2 D Ë | 7cit,m42 □□□ba'H b - 2/ KS54HCTLS 0 /1 KS74HCTLS Dual 4-Input NAND Gates FEATURES DESCRIPTION • Function, pln-out, speed and drive compatibility with 54f74LS logic family • Low power consumption characteristic of C M O S
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KS54HCTLS
KS74HCTLS
54f74LS
7Tb414S
90-XO
14-Pin
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74163 four bit binary counter
Abstract: LS162A 74163 pin configuration counter diagram 74161 162 bcd 74160 function table pin diagram of 74163 pin diagram of 74160 74LS163A equivalent LS160A
Text: 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A S ig n e tic s Counters '160, '162 BCD Decade Counter '161, '163 4-Bit Binary Counter Logic Products Product Specification FEATURES • Synchronous counting and loading • Two Count Enable Inputs for nbit cascading
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LS160A,
LS161A,
LS162A,
LS163A
74LS160A,
74LS162A)
74LS161A,
74LS163A)
54LS/74LS
S4LS/74LS
74163 four bit binary counter
LS162A
74163 pin configuration
counter diagram 74161
162 bcd
74160 function table
pin diagram of 74163
pin diagram of 74160
74LS163A equivalent
LS160A
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MD74HCT240RE
Abstract: 240R 74LS240 MD54HCT240RC TP13a H Driver 16 Pin DIP
Text: hhh MPPP WID54/74WCI24ÔR Inverting O cta liin « Dri v*f/Buffer February'85 Features CONNECTION D IA G R A M D IP T O P V IEW • High latch-up immunity • High current outputs can drive 30 LSTTLloads • Low power ISO-CMOS technology •Bus oriented 3-state outputs
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M054/74WCT240R
74LS240
MD54/74HCT24Ã
MD54HCT240RC,
MD74HCT240RE,
MD74HCT240RE
240R
MD54HCT240RC
TP13a
H Driver 16 Pin DIP
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74HCTLS
Abstract: shiftregisters
Text: SAMSUNG SEMICONDUCTOR I N C OS ODPbSb3 fi 8-Bit Shift-Registers with Input Latches KS54HCTLS KS74HCTLS FEATURES DESCRIPTION • 8-Blt Parallel Storage Register Inputs The *597 consists of an 8-bit storage latch feeding a parallei-ln, serlal-out 8-bit shift register. Both the storage
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KS54HCTLS
KS74HCTLS
7Tb414S
90-XO
14-Pin
74HCTLS
shiftregisters
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OBP16
Abstract: No abstract text available
Text: M OTOROLA D E S C R I P T I O N — The L ST T L / M S1 S N 5 4 L S / 7 4 L S 2 5 7 A an d the S N 5 4 L S / 7 4 L S 2 5 8 A are Q u ad 2-Input Multiplexers with 3-state outputs. Four bits of data from two sou rces can be selected u sin g a C om m on D ata Select input. The four outputs present the selected data
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VM 688
Abstract: KS74HCTL
Text: SAMS UNG SE MICON DU CT OR INC 05 ! s g g * r ?r D eT| ODDbS^ ? >"/7 8-Bit Identity Comparators FEATURES DESCRIPTION • Compares Two 8-BH Words • Choice ol Totem-pole ’688 end open-draln (’689) outputs (’688 Is identical to ’521) • Function, pin-out, speed and drive compatibility with
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7Tb414S
90-XO
14-Pin
VM 688
KS74HCTL
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06A06
Abstract: No abstract text available
Text: SAMSUNG S E M I CON DU CT OR INC "□S DE § 7'ib 414 E ÖDDLMIB H | Dual 1-61-4 Data Selectors/Multiplexers with 3-State Outputs KS54HCTLS O C O KS74HCTLS FEATURES DESCRIPTION • • • • Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection
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KS54HCTLS
KS74HCTLS
7Tb414S
90-XO
14-Pin
06A06
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