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    54LS113A Search Results

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    Part ECAD Model Manufacturer Description Download Buy
    54LS113A/BCA Rochester Electronics LLC 54LS113A - FLIP-FLOP, JK, DUAL, WITH PRESET AND CLEAR - Dual marked (M38510/30104BCA) Visit Rochester Electronics LLC Buy
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    54LS113A Price and Stock

    Motorola Semiconductor Products 54LS113A/BCAJC

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    Bristol Electronics 54LS113A/BCAJC 80
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    Rochester Electronics LLC 54LS113A/BCA

    54LS113A - FLIP-FLOP, JK, DUAL, WITH PRESET AND CLEAR - Dual marked (M38510/30104BCA)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Rochester Electronics 54LS113A/BCA 1,247 1
    • 1 $72.35
    • 10 $72.35
    • 100 $68.01
    • 1000 $61.5
    • 10000 $61.5
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    54LS113A Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54LS113A/BCAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS113A/BDAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS113AM/B2AJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF

    54LS113A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    TSMC 0.18 um MOSfet

    Abstract: M38510 10102BCA IDT7204L 5962-8768401MQA 0.18um LDMOS TSMC sl1053 TSMC 0.25Um LDMOS UT63M125BB SMD RTAX250S-CQ208 5962-04221
    Text: DSCC Supplemental Information Sheet for Electronic QML-38535 Specification Details: Date: 9/2/2008 Specification: MIL-PRF-38535 Title: Advanced Microcircuits Federal Supply Class FSC : 5962 Conventional: No Specification contains quality assurance program: Yes


    Original     		PDF QML-38535 MIL-PRF-38535 MIL-STD-790 MIL-STD-690 -581DSCC QML-38535 TSMC 0.18 um MOSfet M38510 10102BCA IDT7204L 5962-8768401MQA 0.18um LDMOS TSMC sl1053 TSMC 0.25Um LDMOS UT63M125BB SMD RTAX250S-CQ208 5962-04221

    pr 5104

    Abstract: UTRX
    Text: ^ M O T O R O L A M ilitary 54LS 113A Dual J-K Flip-Flop W ith P reset MPO lllllll ELECTRICALLY TESTED PER: MIL-M-38510/30104 The 54LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH,


    OCR Scan     		PDF MIL-M-38510/30104 54LS113A JM38510/30104BXA 54LS113A/BXAJC pr 5104 UTRX

    Untitled

    Abstract: No abstract text available
    Text: M M O T O R O L A Military 54LS113A Dual J-K Flip-Flop With Preset M ELECTRICALLY TESTED PER: MIL-M-38510/30104 P O m in i T h e 5 4 L S 1 1 3 A o ffe r s in d iv id u a l J , K , s e t, a n d c lo c k in p u ts . T h e s e m o n o lith ic d u a l flip -flo p s a r e d e s ig n e d s o th a t w h e n th e c lo c k g o e s H I G H ,


    OCR Scan     		PDF 54LS113A MIL-M-38510/30104 JM38510/30104BXA 54LS113A/BXAJC

    motorola ic 6116

    Abstract: No abstract text available
    Text: M m o to r o la Military 54LS113A D u a l J -K Flip -Flo p W ith P re se t ELECTRICALLY TESTED PER: MIL-M-38510/30104 The 54LS113A o ffe rs in d ivid u a l J, K, set, and clock in p u ts. These m o n o lith ic dual flip -flo p s are designed so th a t w hen th e clock goes


    OCR Scan     		PDF 54LS113A MIL-M-38510/30104 54LS113A JM38510/30104BXA 54LS1F, motorola ic 6116

    SN54S113

    Abstract: SN74LS113A SN54LS113A SN74 SN74S113A
    Text: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISED MARCH 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS113A . S N 54S 113 . . . J OR W PACKAGE SN 74LS 113A . S N 74S 113A . . . O OR N PACKAGE


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113A D2661, SN54S113 SN74LS113A SN54LS113A SN74

    S113

    Abstract: SN54LS113A SN54S113 SN74 SN74LS113A SN74S112 SN74S113
    Text: TYPES 54LS113A, SN54S113, SN74LS113A, SN74S113 DUAL J -K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET REVISED DECEMBER 1983 F u lly B u ffe re d to O ffe r M a x im u m Isola tio n fro m E xtern al D is tu rb a n c e S N 5 4 L S 1 1 3 A , S N 5 4 S 1 1 3 . . . J OR W PACKAG E


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113 S113 SN54LS113A SN54S113 SN74 SN74LS113A SN74S112

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA M ilitary 5 4 LS 7 3 A Dual J-K Flip-Flop With Clear ELECTRICALLY TESTED PER: MIL-M-38510/30101 The 54LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that w hen the clock goes HIGH, the inputs are enabled and data will be accepted. The logic of the J and K inputs may


    OCR Scan     		PDF MIL-M-38510/30101 54LS73A JM38510/30101BXA 54LS73A/BXAJC 54LS113A

    SN74ALS123

    Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
    Text: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS


    OCR Scan     		PDF MIL-M-38510 SN74ALS123 SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138

    74s113a

    Abstract: SN74LS113 74ls113a
    Text: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISEO MARCH 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 3 A , S N 5 4 S 1 1 3 . . . J OR W P A C K A G E


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113A D2661, 74s113a SN74LS113 74ls113a

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		PDF 24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA M ilita ry 54L S 73A Dual J-K Flip-Flop W ith C lear ELECTRICALLY TESTED PER: MIL-M-38510/30101 M mini The 5 4 L S 7 3 A offers individual J, K, clear, and clock inputs. These dual flip -flo p s are desig n ed so th a t w hen the clo ck g oe s HIG H , th e inputs


    OCR Scan     		PDF MIL-M-38510/30101 JM38510/30101BXA 54LS73A/BXAJC

    Untitled

    Abstract: No abstract text available
    Text: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISED MARCH 1988 Fully Buffered to Offer Meximum Isolation from External Disturbance SNS4LS113A. SN54S113 . . . J OR W PACKAGE SN74LS113A. SN74S113A . . . O OR N PACKAGE


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113A D2661, SNS4LS113A. SN54S113 SN74LS113A. 54LS1

    SN74LS113A

    Abstract: No abstract text available
    Text: TYPES 54LS113A, SN54S113, SN74LS113A, SN74S113 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET REVISED DECEMBER 1983 Fully Buffered to O ifer M axim um Isolation fro m External Disturbance S N 54LS 113A , S N 54S 113 . . . J OR W PACKAGE S N 74LS 113A , S N 74S 113 . . D , J OR N PACKAGE


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113 SN74LS113A

    DM54

    Abstract: DM74 DM74LS113A FTHA
    Text: 54LS113A/DM74LS113A National Semiconductor 54LS113A/DM74LS113A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs General Description Absolute Maximum Ratings Note d T h is d e vice c o n ta in s tw o in d e p e n d e n t neg a tive -ed g e trig g e re d J-K flip -flo p s w ith c o m p le m e n ta ry o u tp u ts .


    OCR Scan     		PDF DM54LS113A/DM74LS113A 25Vand 25Vfor DM54 DM74 DM74LS113A FTHA