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    64-POINT XILINX Search Results

    64-POINT XILINX Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TCR5RG28A Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 2.8 V, 500 mA, WCSP4F Visit Toshiba Electronic Devices & Storage Corporation
    TCR3DM18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 300 mA, DFN4 Visit Toshiba Electronic Devices & Storage Corporation
    TCR3DG18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 300 mA, WCSP4E Visit Toshiba Electronic Devices & Storage Corporation
    TCR2EF18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 200 mA, SOT-25 (SMV) Visit Toshiba Electronic Devices & Storage Corporation
    TCR3RM28A Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 2.8 V, 300 mA, DFN4C Visit Toshiba Electronic Devices & Storage Corporation

    64-POINT XILINX Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    verilog for 8 point fft

    Abstract: vhdl for 8 point fft xlinx virtex 16 point FFT radix-4 VHDL 64-point mrd 148 system generator fft XCV300 z transform in control theory
    Text: 64-Point Complex FFT/IFFT V1.0.3 December 17, 1999 Product Specification R Functional Description Features The vFFT64 fast Fourier transform FFT Core computes a 64-point complex forward FFT or inverse FFT (IFFT). The input data is a vector of 64 complex values represented as


    Original     		64-Point vFFT64 16-bit 16-bits verilog for 8 point fft vhdl for 8 point fft xlinx virtex 16 point FFT radix-4 VHDL mrd 148 system generator fft XCV300 z transform in control theory PDF

    64 point FFT radix-4

    Abstract: 64 point radix 4 FFT 64-POINT xilinx radix4 radix-4 64-point ifft QSC family CORE i3 block diagram Fourier transform
    Text: CS2460 TM 64-Point Pipelined FFT/IFFT Virtual Components for the Converging World The CS2460 is an online programmable, pipelined architecture 64-Point FFT/IFFT core. This highly integrated application specific core computes the FFT/IFFT based on a radix-4 decimation in frequency DIF algorithm. It


    Original     		CS2460 64-Point CS2460 DS2460 64 point FFT radix-4 64 point radix 4 FFT 64-POINT xilinx radix4 radix-4 ifft QSC family CORE i3 block diagram Fourier transform PDF

    RM5200

    Abstract: MIC29302 footprint 304-SBGA Quantum Effect Devices vero PK100 IPC-D-317B QUANTUM CAPACITIVE LT1085CT LT1584 qed rm5200
    Text: PCB Design Notes for the RM7000 Application Note Introduction The RM7000 is a 64-bit MIPS IV Instruction Set Architecture CPU with 48/64-entry TLB memory management unit, double precision floating point unit, a 64-bit multiplexed address and data bus which is capable of operating at up to 125 MHz .


    Original     		RM7000 RM7000 64-bit 48/64-entry 128KB 304-ball RM5200 MIC29302 footprint 304-SBGA Quantum Effect Devices vero PK100 IPC-D-317B QUANTUM CAPACITIVE LT1085CT LT1584 qed rm5200 PDF

    MityDSP

    Abstract: TMS6711 EMIF sdram full example code XC3S400 IOC15 EMIF sdram full example
    Text: Critical Link, LLC www.criticallink.com MityDSP MityDSP Processor Card 28-AUG-2007 FEATURES • TI TMS320C6711 Digital Signal Processor - 200 MHz - Hardware Floating Point Unit - 64 KB L2 cache - 2 Integrated McBSPs - JTAG Emulation/Debug • On-Board Xilinx FPGA


    Original     		TMS320C6711 XC3S400 28-AUG-2007 21-APR-2007 28-AUG-2007 MityDSP TMS6711 EMIF sdram full example code IOC15 EMIF sdram full example PDF

    Xilinx XC3S1000

    Abstract: TMS6711 EMIF sdram full example code EMIF sdram full example lwIP Xilinx usb jtag cable
    Text: Critical Link, LLC www.criticallink.com MityDSP-XM MityDSP-XM Processor Card 28-AUG-2007 FEATURES • TI TMS320C6711 Digital Signal Processor - 200 MHz - Hardware Floating Point Unit - 64 KB L2 cache - 2 Integrated McBSPs - JTAG Emulation/Debug • On-Board Xilinx FPGA


    Original     		TMS320C6711 XC3S1000 28-AUG-2007 21-APR-2007 28-AUG-2007 Xilinx XC3S1000 TMS6711 EMIF sdram full example code EMIF sdram full example lwIP Xilinx usb jtag cable PDF

    verilog for 8 point fft

    Abstract: vhdl for 8 point fft vhdl for 8 point fft in xilinx fft algorithm mrd 148 64-POINT XCV300 64-POINT xilinx 16 point FFT radix-4 VHDL IFFT
    Text: High-Performance 64-Point Complex FFT/IFFT V1.0.3 Dec17 1999 Product Specification Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 FAX: +1 408-559-7114 Email: coregen@xilinx.com URL: http://www.xilinx.com/ipcenter 1 Features • •


    Original     		64-Point Dec17 64-point 16-bit verilog for 8 point fft vhdl for 8 point fft vhdl for 8 point fft in xilinx fft algorithm mrd 148 XCV300 64-POINT xilinx 16 point FFT radix-4 VHDL IFFT PDF

    verilog for 8 point fft

    Abstract: em 18 reader module pin diagram 64-POINT XCV300 vhdl for 8 point fft in xilinx 64 point fft xilinx block ifft em 18 reader module v2.0 application of radix 2 inverse dif fft 64-POINT xilinx
    Text: High-Performance 64-Point Complex FFT/IFFT V2.0 July 5 2000 Product Specification Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 FAX: +1 408-559-7114 Email: coregen@xilinx.com URL: http://www.xilinx.com/ipcenter 1 Features • •


    Original     		64-Point 64-point 16-bit verilog for 8 point fft em 18 reader module pin diagram XCV300 vhdl for 8 point fft in xilinx 64 point fft xilinx block ifft em 18 reader module v2.0 application of radix 2 inverse dif fft 64-POINT xilinx PDF

    64 point FFT radix-4

    Abstract: em 18 reader module pin diagram verilog for 8 point pipeline fft core diF fft algorithm VHDL 64-POINT XCV300 64-POINT xilinx 16 point FFT radix-4 VHDL 64 point fft xilinx
    Text: High-Performance 64-Point Complex FFT/IFFT V1.0.5 July 5 2000 Product Specification Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 FAX: +1 408-559-7114 Email: coregen@xilinx.com URL: http://www.xilinx.com/ipcenter 1 Features • •


    Original     		64-Point 64-point 16-bit 64 point FFT radix-4 em 18 reader module pin diagram verilog for 8 point pipeline fft core diF fft algorithm VHDL XCV300 64-POINT xilinx 16 point FFT radix-4 VHDL 64 point fft xilinx PDF

    16 point DIF FFT using radix 4 fft

    Abstract: 1024-POINT 64 point FFT radix-4 8 point fft xilinx DPM 3 18x18-Bit
    Text: High-Performance 64-,256-,1024-point Complex FFT/IFFT V1.1 Nov 1, 2002 Product Specification Theory of Operation The fast Fourier transform FFT is a computationally efficient algorithm for computing a discrete Fourier transform (DFT). The DFT X ( k ), k = 0,… , N − 1 of a sequence


    Original     		1024-point 16 point DIF FFT using radix 4 fft 1024-POINT 64 point FFT radix-4 8 point fft xilinx DPM 3 18x18-Bit PDF

    XC2V1000-FG456

    Abstract: XC2V1000fg456 XC2V1000FG XC2VP40FF1152-6C XC2V1000FG456-5C 34h 751 V5078 XC2VP20FF1152-6C Virtex-II user guide
    Text: LogiCORE PCI-X Interface v5.0 DS 208 April 26, 2004 Introduction Product Specification v5.0.78 LogiCORE Facts With the Xilinx LogiCORE PCI-X Interface, a designer can build a customized PCI-X 2.0 mode1-compliant core with high sustained performance, 1066 MB/sec.


    Original     		PCI-X64/66 PCI64/33 64-bit, XC2VP7FF672-6 XC2VP20FF1152-6C XC2VP30. XC2VP50. XC2V1000-FG456 XC2V1000fg456 XC2V1000FG XC2VP40FF1152-6C XC2V1000FG456-5C 34h 751 V5078 Virtex-II user guide PDF

    XC4VLX25-FF668-10C

    Abstract: XC5VLX50TFF1136 XC5VLX110T-ff1136 XC5VLX50T-FF1136 XC5VSX95TFF1136 XC5VLX110TFF1136 XC5VLX110-FF1153 XC5VFX70TFF1136 XC4VLX25-FF668 XC5VFX70T-FF1136-1C
    Text: Initiator/Target v5 & v6 for PCI-X DS208 April 24, 2009 Product Specification v5.166 & v6.8 Features Core Facts v6 PCI64/33 Mode Only • Fully verified design tested with Xilinx proprietary test bench and hardware LUTs 1748 1469 2310 1868 Slice Flip Flops


    Original     		DS208 PCI64/33 XC4VLX25-FF668-10C XC5VLX50TFF1136 XC5VLX110T-ff1136 XC5VLX50T-FF1136 XC5VSX95TFF1136 XC5VLX110TFF1136 XC5VLX110-FF1153 XC5VFX70TFF1136 XC4VLX25-FF668 XC5VFX70T-FF1136-1C PDF

    80C31 instruction set

    Abstract: xc2s200 pq208 xilinx code for 8-bit serial adder dvb-RCS transmitter XC2S50 driver PIC Microcontroller GSM Modem POS-PHY ATM format dvb-RCS modulator uart 16450 128-bit key generation matlab code for image enc
    Text: XILINX IP SELECTION GUIDE Implementation Example Function Communication & Networking BUFE-based Multiplexer Slice 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder 8b/10b Decoder 8b/10b Encoder


    Original     		8b/10b DO-DI-ADPCM32) DO-DI-ADPCM64) CC-201) CC-200) CRC10 CC-130) CRC32 CC-131) 80C31 instruction set xc2s200 pq208 xilinx code for 8-bit serial adder dvb-RCS transmitter XC2S50 driver PIC Microcontroller GSM Modem POS-PHY ATM format dvb-RCS modulator uart 16450 128-bit key generation matlab code for image enc PDF

    80C31 instruction set

    Abstract: XC2S200 pq208 xilinx fifo generator 6.2 application of 8259 microcontroller design BCD adder pal dvb-RCS modem hitachi pbx AX1610 MC68000 opcodes adder xilinx
    Text: Vendor Name IP Type Xilinx Xilinx Xilinx sysonchip Xilinx Xilinx Amphion Amphion Amphion Amphion Amphion Xilinx Xilinx NewLogic LogiCORE LogiCORE LogiCORE AllianceCORE LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiCORE


    Original     		8b/10b DO-DI-ADPCM32) DO-DI-ADPCM64) CC-201) CC-200) CRC10 CC-130) CRC32 CC-131) 80C31 instruction set XC2S200 pq208 xilinx fifo generator 6.2 application of 8259 microcontroller design BCD adder pal dvb-RCS modem hitachi pbx AX1610 MC68000 opcodes adder xilinx PDF

    xilinx vhdl code for floating point square root

    Abstract: multiplier accumulator MAC code verilog multi channel UART controller using VHDL 80C31 instruction set vhdl code of 32bit floating point adder verilog code for floating point adder xilinx logicore fifo generator 6.2 xilinx vhdl code for floating point square root o vhdl code for 3-8 decoder using multiplexer vhdl code 32bit LFSR
    Text: R Using the CORE Generator System Introduction This section on the Xilinx CORE Generator System and the Xilinx Intellectual Property IP Core offerings is provided as an overview of products that facilitate the Virtex-II design process. For more detailed and complete information, consult the CORE Generator


    Original     		XC2V1000-4 UG002 xilinx vhdl code for floating point square root multiplier accumulator MAC code verilog multi channel UART controller using VHDL 80C31 instruction set vhdl code of 32bit floating point adder verilog code for floating point adder xilinx logicore fifo generator 6.2 xilinx vhdl code for floating point square root o vhdl code for 3-8 decoder using multiplexer vhdl code 32bit LFSR PDF

    precision Sine Wave Generator

    Abstract: sine cosine function generator XC4000 XC4000E X8140
    Text: dsp_trigtabl.fm Page 75 Wednesday, March 4, 1998 3:36 PM Sine/Cosine March 16, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL: www.xilinx.com format. However, values for theta may be provided in either


    Original     		PDF

    radix-2 fft xilinx

    Abstract: BUTTERFLY DSP 64 point radix 4 FFT 8 point fft 8 point fft xilinx Butterfly Distributed arithmetic data path blocks for Radix - 2 butterfly 16 point FFT butterfly 8-point xilinx FFT radix-2
    Text: The Fastest FFT in the West The incorporation of a large FFT [1] in a single FPGA, while noteworthy, may evoke a “so what” response. Again its speed will be compared to the more standard single chip DSP design. We propose to compare Xilinx FPGA performance with an exhaustive list of DSP devices. The test benchmark fig. 1 ,


    Original     		320nsecs) radix-2 fft xilinx BUTTERFLY DSP 64 point radix 4 FFT 8 point fft 8 point fft xilinx Butterfly Distributed arithmetic data path blocks for Radix - 2 butterfly 16 point FFT butterfly 8-point xilinx FFT radix-2 PDF

    vhdl code for carry select adder using ROM

    Abstract: vhdl code for 8-bit serial adder 8 bit carry select adder verilog code xilinx code fir filter in vhdl single port ram testbench vhdl 16 bit carry select adder verilog code XC2064 fir vhdl code new ieee programs in vhdl and verilog verilog code for fir filter
    Text: March 23, 1998 CORE Generator User Guide version 1.4 CORE Generator 1.4 User Guide R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Archindry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc.


    Original     		XC2064, XC3090, XC4005, XC-DS501, 028expg299-2 XC4028EX PG299 vhdl code for carry select adder using ROM vhdl code for 8-bit serial adder 8 bit carry select adder verilog code xilinx code fir filter in vhdl single port ram testbench vhdl 16 bit carry select adder verilog code XC2064 fir vhdl code new ieee programs in vhdl and verilog verilog code for fir filter PDF

    Untitled

    Abstract: No abstract text available
    Text: BUFE-Based Multiplexer Slice V3.0 November 3, 2000 Product Specification • • • Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: support.xilinx.com 1 to 64 inputs Incorporates Xilinx Smart-IP technology for maximum


    Original     		PDF

    DX-DI-64IP-XVE

    Abstract: PCI64
    Text: LogiCORE PCI Interface v3.0 DS 208 v.1.2 June 28, 2002 Data Sheet, v3.0.99 Introduction LogiCORE Facts With the Xilinx LogiCORE PCI-X Interface, a designer can build a customized PCI-X 1.0a-compliant core with high sustained performance, 800 Mbytes/sec.


    Original     		PCI-X64 PCI64 DX-DI-64IP-XVE PDF

    Untitled

    Abstract: No abstract text available
    Text: BUFT-Based Multiplexer Slice V2.0 June 30, 2000 Product Specification R Features • Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/support/techsup/appinfo www.xilinx.com/ipcenter • • •


    Original     		x9051 PDF

    Multiplexor 64 inputs

    Abstract: No abstract text available
    Text: buft_mux_slice.fm Page 1 Sunday, November 5, 2000 3:24 PM BUFT-Based Multiplexer Slice V3.0 November 3, 2000 Product Specification Features • Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: BUFE-Based Multiplexer Slice V2.0 June 30, 2000 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/support/techsup/appinfo www.xilinx.com/ipcenter Features • • • •


    Original     		PDF

    xc6slx150t

    Abstract: STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2
    Text: LogiCORE IP Fast Fourier Transform v8.0 DS808 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the


    Original     		DS808 xc6slx150t STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2 PDF

    str 5653

    Abstract: STR - Z 2757 STR M 6545 16 point FFT radix-4 VHDL documentation radix-2 DIT FFT vhdl program STR G 5653 STR F 5653 xc6slx150t RTL 8376 matlab code for radix-4 fft
    Text: Fast Fourier Transform v7.0 DS260 June 24, 2009 Product Specification Introduction Overview The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the Discrete Fourier Transform (DFT).


    Original     		DS260 str 5653 STR - Z 2757 STR M 6545 16 point FFT radix-4 VHDL documentation radix-2 DIT FFT vhdl program STR G 5653 STR F 5653 xc6slx150t RTL 8376 matlab code for radix-4 fft PDF