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    Untitled

    Abstract: No abstract text available
    Text: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose


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    DS4510 64byte 400kbps) 100kbps) 125ms 1000ms U10-2* 21-0061I DS4510U-5 PDF

    DS4510

    Abstract: DS4510U-10 DS4510U-15 DS4510U-5 J-STD-020A
    Text: Rev 1; 6/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose


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    DS4510 64byte 400kbps) 100kbps) 125ms 1000ms DS4510U-10 DS4510U-15 DS4510U-5 J-STD-020A PDF

    DS4510U-5

    Abstract: J-STD-020A DS4510 DS4510U-10 DS4510U-15
    Text: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose


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    DS4510 64byte 400kbps) 100kbps) 125ms 1000ms DS4510U-5 J-STD-020A DS4510U-10 DS4510U-15 PDF

    usop-10

    Abstract: No abstract text available
    Text: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose


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    DS4510 64byte 400kbps) 100kbps) 125ms 1000ms Power-Sup21-0061I U10-2* 21-0061I usop-10 PDF

    Untitled

    Abstract: No abstract text available
    Text: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I2C interface using either fast-mode


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    DS4510 64byte 400kbps) 100kbps) 125ms 1000ms PDF

    transistor f8

    Abstract: DS4510 DS4510U-10 DS4510U-15 DS4510U-5 J-STD-020A
    Text: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I2C interface using either fast-mode


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    DS4510 64byte 400kbps) 100kbps) 125ms 1000ms transistor f8 DS4510U-10 DS4510U-15 DS4510U-5 J-STD-020A PDF

    mip 291

    Abstract: mip 290
    Text: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)


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    SMJ320C80 SGUS025 32-Bit IEEE-754 64-Bit TMS320C8X SPRA269 mip 291 mip 290 PDF

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA Original CMOS 8-Bit Microcontroller TLCS-870/C Series TMP86FM25FG Semiconductor Company TMP86FM25 Document Change Notification The purpose of this notification is to inform customers about the launch of the Pb-free version of the device. The introduction of a Pb-free replacement affects the datasheet. Please understand that this


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    TLCS-870/C TMP86FM25FG TMP86FM25 TMP86FM25) 86FM25-50 PDF

    TXC07900AIBG

    Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
    Text: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary


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    OED155 TXC-07900 TXC-07900-MB, OED155TM TXC07900AIBG TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117 PDF

    TranSwitch Corporation

    Abstract: B2M1-5
    Text: PHAST-1 Device SONET STS-1 Overhead Terminator TXC-06101 DATA SHEET • Provides SONET interface to any type of payload • Programmable STS-1 or STS-N modes • Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse for


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    TXC-06101 TXC-06101-MB TranSwitch Corporation B2M1-5 PDF

    DF2-A

    Abstract: XB2H DF2E
    Text: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte wide drop and add buses


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    TXC-03453 TXC-03453-MB DF2-A XB2H DF2E PDF

    Untitled

    Abstract: No abstract text available
    Text: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte-wide drop and add buses


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    TXC-03453 TXC-03453-MA PDF

    VTXP-6

    Abstract: TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822
    Text: VTXP-6 Device STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 DATA SHEET PRELIMINARY TXC-06951-MB, Ed. 5 March 2006 FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.


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    TXC-06951 TXC-06951-MB, TU-11/TU-12/TU-3/ VTXP-6 TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822 PDF

    Y446

    Abstract: Y443 y441 POP-12 B1 Y447 Y442
    Text: POP-12 Device OC-12 SONET/SDH Path Overhead Processor, Retimer, and Cross Connect TXC-06603 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Path overhead POH processing for up to 12 x STS-1 SPEs or 4 x VC-4/STS-3c SPEs • 4 Tx and 4 Rx Pointer Tracking State Machines


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    POP-12TM OC-12 TXC-06603 TXC-06603-MB Y446 Y443 y441 POP-12 B1 Y447 Y442 PDF

    TH4B

    Abstract: No abstract text available
    Text: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET • • • • • • • • • • • • • • • • • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis


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    TXC-06103 64-byte TXC-06103-MB TH4B PDF

    TUG-3

    Abstract: vc-4 digital cross connect
    Text: TL3M Device Triple Level 3 Mapper TXC-03453B TECHNICAL OVERVIEW Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal


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    TXC-03453B TXC-03453B-MA TUG-3 vc-4 digital cross connect PDF

    A1515-1

    Abstract: No abstract text available
    Text: EtherMap -48 Device OC-48 SONET/SDH Ethernet Mapper TXC-06710 TECHNICAL OVERVIEW PRODUCT PREVIEW TERMINAL SIDE Control & Clock EEPROM Signals Serial Interface EtherMap™-48 TXC-06710 is a highly-integrated device for mapping IEEE 802.3 100/1000 Mbps Ethernet and block encoded


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    EtherMapTM-48 OC-48 TXC-06710 STS-48/STM-16 STS-12/STM-4 AU-4-16c/AU-4-4c/AU-4/AU-3 OC-12/4x STS48-SPE/STS-48c-copyright, TXC-06710-MA, A1515-1 PDF

    Untitled

    Abstract: No abstract text available
    Text: TL3M Device Triple Level 3 Mapper TXC-03453 TECHNICAL OVERVIEW SDH/SONET SIDE TELECOM BUS O-Bit Interfaces • Add/drop multiplexers • Digital cross connect systems • Broadband switching systems • Transmission equipment External Alarm Interfaces Drop Bus


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    TXC-03453 TXC-03453-MA PDF

    Untitled

    Abstract: No abstract text available
    Text: Sertopia Device UTOPIA Serializer TXC-05860 DATA SHEET PRODUCT PREVIEW The Sertopia™ TXC-05860 UTOPIA serializer is a single-chip solution for broadband communication systems. A pair of Sertopia devices interface two remote UTOPIA ports transparently across a serial link. The Sertopia emulates a


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    TXC-05860 off-li05860-MB PDF

    MC 4011 BCP

    Abstract: PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT
    Text: EtherPHAST -24 Device 2x OC-12/STM-4 SONET/SDH Ethernet Mapper TXC-06745 DATA SHEET TXC-06745-MB, Ed. 2 February 2006 FEATURES APPLICATIONS • Client Interfaces: 2x GMII/24x SMII/4x TBI/MPI 24 channel packet all pin shared • Two serial Gigabit Ethernet (1.25 Gbit/s) ports with integrated CRSU/SerDes (8B/10B)


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    OC-12/STM-4 TXC-06745 TXC-06745-MB, GMII/24x 8B/10B) 8B/10B 32-bit EtherPHAST-24 MC 4011 BCP PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT PDF

    Untitled

    Abstract: No abstract text available
    Text: PHAST -12N Device STM-4/OC-12 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06312 DESCRIPTION • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis - single 622.08 Mbit/s STM-4/OC-12 signal or - four 155.52 Mbit/s STM-1/OC-3 signals


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    STM-4/OC-12 TXC-06312 VC-4-Xc/STS-1/STS-3c/STC-6c/STS9c/STS-12c TXC-06312-MB PDF

    Untitled

    Abstract: No abstract text available
    Text: NRND: Not recommended for new designs. TE X AS I NS TRUM E NTS - P RO DUCTION D ATA Stellaris LM3S1B21 Microcontroller D ATA SHE E T D S -LM3S 1B 21 - 1 3 4 4 2 . 2 5 4 9 S P M S 222H C o p yri g h t 2 0 07-2012 Te xa s In stru me n ts In co rporated


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    LM3S1B21 PDF

    Untitled

    Abstract: No abstract text available
    Text: New Product Highlights TL16C750 Extended FIFO Asynchronous Communications Element I Description The TL16C750 performs parallel-to-serial and serial-to parallel conversion on data characters transmitted to and from the CPU. The ’750 features a 64-byte FIFO, in


    OCR Scan
    TL16C750 TL16C750 64-byte TL16C550C 16-byte TL16C750FN 44-pin TL16C750PM 64-pin PDF

    TMS34061FNL

    Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
    Text: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW


    OCR Scan
    32-Bit 128-Megabyte 16-Bit 64-Bit 256-Byte TMS34061FNL lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625 PDF