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Catalog Datasheet	MFG & Type	PDF	Document Tags
verilog code for dual port ram with axi interface Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0 Text: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories	Original	PDF	DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
ZL50074 Abstract: STOD03 Motorola P13 - 02.08.00 Text: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features January 2004 • 32,768 channel x 32,768 channel non-blocking digital TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking	Original	PDF	ZL50074 ZL50074 STOD03 Motorola P13 - 02.08.00
ZL80009 Abstract: ZL50075 Text: ZL50075 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams 8, 16, 32 or 64 Mbps , and 64 Inputs and 64 Outputs Data Sheet Features • January 2004 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at	Original	PDF	ZL50075 ZL80009
MLP8 2x3mm Abstract: MLP8 m25p64 MARKING code mf stmicroelectronics AN2043 SO8 NARROW Part Marking STMicroelectronics flash memory EEPROM 16Mb M25P stmicroelectronics eeprom M25P16 Text: Serial EEPROM, serial Flash and application specific serial non-volatile memories Selection guide February 2005 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties	Original	PDF	SGEEFLASH/1204 MLP8 2x3mm MLP8 m25p64 MARKING code mf stmicroelectronics AN2043 SO8 NARROW Part Marking STMicroelectronics flash memory EEPROM 16Mb M25P stmicroelectronics eeprom M25P16
XC6SL Abstract: SPARTAN 6 Configuration SPARTAN-6 DS512 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18 Text: Block Memory Generator v3.3 DS512 September 16, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.	Original	PDF	DS512 XC6SL SPARTAN 6 Configuration SPARTAN-6 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18
ZL50073 Abstract: No abstract text available Text: ZL50073 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams 8, 16, 32 or 64 Mbps , and 128 Inputs and 128 Outputs Data Sheet Features • January 2004 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at	Original	PDF	ZL50073 ZL50073GA ZL50073
RAMB16BWER Abstract: vhdl code hamming ecc 8kx1 RAM XC6VLX365T-FF1759-1 Xilinx Virtex6 Design Kit vhdl code hamming DS512 RAMB36 verilog code hamming vhdl spartan 3a Text: Block Memory Generator v3.2 DS512 June 24, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.	Original	PDF	DS512 RAMB16BWER vhdl code hamming ecc 8kx1 RAM XC6VLX365T-FF1759-1 Xilinx Virtex6 Design Kit vhdl code hamming RAMB36 verilog code hamming vhdl spartan 3a
cd 40278 Abstract: ZL800 ZL8000 ZL80009 ZL50075 Text: ZL50075 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams 65, 32, 16 or 8 Mbps , and 64 inputs and 64 outputs Data Sheet Features • December 2003 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at	Original	PDF	ZL50075 cd 40278 ZL800 ZL8000 ZL80009
STiD12 Abstract: No abstract text available Text: ZL50073 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams 8, 16, 32 or 64 Mbps , and 128 Inputs and 128 Outputs Data Sheet Features • January 2004 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at	Original	PDF	ZL50073 32ude STiD12
virtex-7 Abstract: verilog code for dual port ram with axi interface AXI4 lite verilog virtex7 XC6SLX25T-2CSG324 DS512 XC6SLX RAMB18SDP 16Kx1 spartan6 block ram Text: LogiCORE IP Block Memory Generator v6.1 DS512 March 1, 2011 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories	Original	PDF	DS512 virtex-7 verilog code for dual port ram with axi interface AXI4 lite verilog virtex7 XC6SLX25T-2CSG324 XC6SLX RAMB18SDP 16Kx1 spartan6 block ram
Untitled Abstract: No abstract text available Text: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features January 2004 • 32,768 channel x 32,768 channel non-blocking digital TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking	Original	PDF	ZL50074
XC5VLX50-FF676 Abstract: ramb16bwer SPARTAN 3an spartan 3a vhdl code for 9 bit parity generator DS512 4VLX60 EE core SPARTAN 3an power of 2 vhdl code for 8 bit parity generator Text: Block Memory Generator v2.6 DS512 October 10, 2007 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.	Original	PDF	DS512 XC5VLX50-FF676 ramb16bwer SPARTAN 3an spartan 3a vhdl code for 9 bit parity generator 4VLX60 EE core SPARTAN 3an power of 2 vhdl code for 8 bit parity generator
ZL8000 Abstract: ZL800 A18-1 MC68000 MC68302 ZL50075 4027f Text: ZL50075 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams 8, 16, 32 or 64 Mbps , and 64 Inputs and 64 Outputs Data Sheet Features • January 2004 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at	Original	PDF	ZL50075 ZL50075GA ZL8000 ZL800 A18-1 MC68000 MC68302 ZL50075 4027f