um61168

Contextual Info: L I8 V 1 C U M 6 1 1 6 8 Series 2 x 4K x 16 CMOS CACHE RAM P R ELIM IN AR Y Features • S ingle + 5 V p o w e r su pp ly ■ ■ Access tim e s: 2 5 /3 5 /4 5 ns m ax. ■ ■ S u p p o rts h ig h speed 8 0 3 8 6 (3 3 /2 5 /2 0 M H z) w it h fa st ■ C u rre n t:

Contextual Info: 74LS295B Signetics Shift Register 4-Bit Shift Register With 3-State Outputs Product Specification Logic Products FEATURES • 4-bit parallel load shift register • Independent 3-State buffer outputs • See '395 for serial expansion and Master Reset version

Contextual Info: GD54/74LS367A HEX BUS DRIVERS WITH 3-STATE OUTPUTS Feature • 3-State Outputs Drive Bus Line or Buffer Memory Address Registers • Choice of True or Inverting Outputs Pin Configuration Vcc G2 6A 6Y 5A 5Y 4A 4Y Description These hex buffers and line drivers are designed

IC 7437

Contextual Info: Signefics I 7437, LS37, S37 Buffers Quad Two-Input NAND Buffer Product Specification Logic Products T Y P IC A L PR O PAG A TIO N DELAY TYPE T Y P IC A L S U P P LY C U R R E N T TO TAL 74 37 1 1ns 22m A 74LS37 12ns 3.5m A 74S37 4ns 33m A ORDERING CODE CO M M ER C IA L R A N G E

M74LS640-1P

Abstract: 251C M74LS640P
Contextual Info: MITSUBISHI LSTTLs M74LS640P OCTAL BUS TR ANSCEIVER W IT H 3-S T A T E O U TPU T IN V E R T E D DESCRIPTION T h e M 7 4 L S 6 4 0 P is a s em ico n d u c to r in teg ra te d c irc u it c o n ­ ta in in g 8 bus tra n s m itte r/re c e iv e r c ircuits w ith in verted

Contextual Info: GD54/74LS368A HEX TRI-STATE INVERTING BUFFERS Description This device contains six independent gates each of which performs an inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capabili­

tc001

Abstract: am2946
Contextual Info: Am2946/Am2947 Am2946/Am2947 Octal Three-State Bidirectional Bus Transceivers DISTINCTIVE CHARACTERISTICS Am 2946 inverting tra nsceivers; Am 2947 noninverting transceivers; Transm it/R eceive and Chip Disable sim pli­ fy control logic Bus port stays in tii-im pedance state during pow er up/

74LS612

Contextual Info: GD54/74LS612 MEMORY MAPPERS WITH 3-STATE MAP OUTPUTS Feature • • Expands 4 A ddress Lines to 12 A ddress Lines Designed fo r Paged M em ory Mapping Pin Configuration 10j V cc 5 ^ MA2 R S 3^ 38 R S I csE 37)MA1 STROBE [ 5 36| RSO R w [][ 3 ^ MAO Descriptions

a2733

Abstract: 74LS622 74LS 74LS621 N74LS621N N74LS622N
Contextual Info: 74LS621, LS622 Signetics Transceivers 'LS621 Non-inverting Octal Bus Transceiver Open Collector ' LS622 Inverting Octal Bus Transceiver (Open Collector) Product Specification Logic Products FEATURES • Octal bidirectional bus interface • Open-collector output

GD74LS373

Contextual Info: GD54LS373/GD74LS373 OCTAL D-TYPE LATCHES; 3-STATE OUTPUTS COMMON OUTPUT CONTROL COMMON ENABLE Feautre • • • • • 8 Latches in a Single Package 3-State Bus-Driving Outputs Full Paralle-Access for Loading Buffered Control Inputs Clock/Enable input Has Hysteresis to Improve

Contextual Info: Am25LS2536 A m 25LS2536 Eight-Bit Decoder with Control Storage DISTINCTIVE CHARACTERISTICS • • • • • • 8-bit decoder/demultiplexer with control storage 3-state outputs Common clock enable Common clear Polarity control Advanced Low-Power Schottky Process

LS640-1

Contextual Info: GD54/74LS640, GD74LS640-1 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUT INVERTED Features Pin Configuration • • Inverting 3-STATE buffer outputs Bi-directional Bus Transceivers in High-Density 20-Pin Packages • Hysteresis at Bus Inputs Improves Noise Margins

Contextual Info: OCTAL BUFFER/LINE DRIVERS/ 1 LINE RECEIVERS NON INVERTED 3-STATE OUTPUTS OUTPUTS Feature • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • • P-N-P Inputs Reduce D-C Loading Hysteresis at Inputs Improves Noise Margins Pin Configuration

ic yo

Contextual Info: Am25LS2536 A m 25LS2536 Eight-Bit Decoder with Control Storage DISTINCTIVE CHARACTERISTICS • • • • • • 8-bit decoder/demultiplexer with control storage 3-state outputs Common clock enable Common clear Polarity control Advanced Low-Power Schottky Process

tc001

Abstract: 1KS3T
Contextual Info: Am2946/Am2947 Am2946/Am2947 Octal Three-State Bidirectional Bus Transceivers DISTINCTIVE CHARACTERISTICS Am 2946 inverting tra nsceivers; Am 2947 noninverting transceivers; Transm it/R eceive and Chip Disable sim pli­ fy control logic Bus port stays in tii-im pedance state during pow er up/

74LS125A

Abstract: ls125a TTL 74125 1N30 signetics 74LS125A
Contextual Info: 74125, 74126, LS125A, LS126A Signefics Buffers Quad 3-State Buffer Product Specification Logic Products TYPE FUNCTION TABLE '125, LS125A INPUTS OUTPUT C A Y L L H L H X L H L H L X Z = = = = OUTPUT C A Y H H L L H X L H (Z) HIGH LOW D o n't HIGH voltage level

IC 74ls373

Abstract: 74LS373 74LS533 74LS373 40 pin SN74LS373N AM25LS533DC 74LS53 Ls373 pin diagram of IC 74LS373 sn54ls373j
Contextual Info: Am25LS373 • Am54LS/74LS373 Am25LS533 • Am54LS/74LS533 Octal Latches with Three-State Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8 latches in a single package • Non-inverting 'LS373, inverting LS533 • Three-state outputs interlace directly with bus organized

GD74LS373

Abstract: GD74LS
Contextual Info: GD54LS373/GD74LS373 OCTAL D-TYPE LATCHES; 3-STATE OUTPUTS COMMON OUTPUT CONTROL COMMON ENABLE Feature • • • • • 8 Latches in a Single Package 3-State Bus-Driving Outputs Full Paralle-Access for Loading Buffered Control Inputs Clock/Enable input Has Hysteresis to Improve

GD74LS373

Abstract: 54LS 74LS LS373 GD74LS
Contextual Info: GD54LS373/GD74LS373 OCTAL D-TYPE LATCHES; 3-STATE OUTPUTS COMMON OUTPUT CONTROL COMMON ENABLE Feautre • 8 Latches in a Single Package • 3-State Bus-Driving Outputs • Full Paralle-Access for Loading • Buffered Control Inputs • Clock/Enable input Has Hysteresis to Improve