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    74194 COUNTER Search Results

    74194 COUNTER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74F779PC Rochester Electronics LLC 74F779 - Binary Counter Visit Rochester Electronics LLC Buy
    54191J/B Rochester Electronics LLC 54191 - Decade Counter Visit Rochester Electronics LLC Buy
    74AC11191DW Rochester Electronics LLC 74AC11191 - Binary Counter Visit Rochester Electronics LLC Buy
    MM74C925N Rochester Electronics LLC 74C925 - Display Driver Counter Visit Rochester Electronics LLC Buy
    9305DM/B Rochester Electronics LLC 9305 - Counter Visit Rochester Electronics LLC Buy

    74194 COUNTER Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    ic 74194

    Abstract: pin diagram of ic 74195 ic 74194 pin configuration 74194 ic pin diagram Pin configuration of IC 74194 IC 74194 logic diagram IC 74195 ml741 74194 function table 74194 shift register
    Text: Am54/74194*Am54/74195 Four-Bit Shift Registers gnmctive Characteristics • Parallel inputs and outputs i Positive edge-triggered clocking i Direct overriding clear • 100% reliability assurance testing in compliance with M IL-STD -883. LOGIC SYMBOLS f u n c t io n a l d e s c r i p t i o n


    OCR Scan     		Am54/74194 Am54/74195 MIL-STD-883. ic 74194 pin diagram of ic 74195 ic 74194 pin configuration 74194 ic pin diagram Pin configuration of IC 74194 IC 74194 logic diagram IC 74195 ml741 74194 function table 74194 shift register PDF

    full adder using ic 74138

    Abstract: full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
    Text: EP1800JC-EV1 EP1800JC-EV1 EVALUATION CHIP • Advanced CHMOS circuitry features low power, high performance, and high noise immunity power consumption, high noise margins, and ease of design. The EP1800 is implemented in a sub 2-micron dual-polysilicon CHMOS floating gate EPROM tech­


    OCR Scan     		EP1800JC-EV1 EPt800 68-pin EP1800JC-EV1 0UT20 0UT21 OUT22 0UT23 full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151 PDF

    counter schematic diagram using 74193

    Abstract: shift register ttl ttl 74194 logic diagram 74194 counter 74193 shift register circuit diagram of 16 bit counter 74194 shift register AT6005 counter schematic diagram 74194 function table
    Text: FPGA 16 Bit Up/Down Counter/Shift Register Introduction The AT6000 Series field programmable gate array FPGA lets the designer implement a synchronous, 16 bit Up/Down Counter/Shift Register that operates at 22 MHz under the worst commercial operating conditions. In


    Original     		AT6000 AT6005 counter schematic diagram using 74193 shift register ttl ttl 74194 logic diagram 74194 counter 74193 shift register circuit diagram of 16 bit counter 74194 shift register counter schematic diagram 74194 function table PDF

    74194 counter

    Abstract: 74194 shift register counter schematic diagram using 74193 shifter using mux circuit diagram of 16 bit counter 74194 74194 datasheet ttl 74193 74193 counter data sheet 74193 application diagrams
    Text: FPGA 16-Bit Up/Down Counter/Shift Register Introduction The AT6000 Series field programmable gate array FPGA lets the designer implement a synchronous, 16-bit Up/Down Counter/Shift Register that operates at 22 MHz under the worst commercial operating conditions. In this circuit is most of the


    Original     		16-Bit AT6000 AT6005 16-Bit 74194 counter 74194 shift register counter schematic diagram using 74193 shifter using mux circuit diagram of 16 bit counter 74194 74194 datasheet ttl 74193 74193 counter data sheet 74193 application diagrams PDF

    7483 4 bit binary full adder

    Abstract: 74151 demultiplexer 74153 full adder 74198 shift register 7483 4 bit binary adder 7483 8 bit binary adder 74155 demultiplexer 74150 multiplexer bcd adder with 74283 4 bit 7483 binary adder
    Text: Digital Circuits 54/74 MSI Series Type Description Prop Delay ns or Max. Op. Freq. (MHz) Available Packages P w r1 Diss (mW) 14 Pin DC CJ 16 Pin CL 54/7442 BCD-to-Decimal Decoder 22 140 X 54/7443 Excess 3-to-Decimal Decoder 22 X X 54/7444 Excess 3 Gray-to-Decimal Decoder


    OCR Scan     		16-to-1 Types--55Â 7483 4 bit binary full adder 74151 demultiplexer 74153 full adder 74198 shift register 7483 4 bit binary adder 7483 8 bit binary adder 74155 demultiplexer 74150 multiplexer bcd adder with 74283 4 bit 7483 binary adder PDF

    74194 shift register

    Abstract: 74194 74193 shift register ttl 74194 logic diagram 74193 74194 function table half-adder by using D flip-flop 74193 counter data sheet Asynchronous up and down counter 74194 datasheet
    Text: 16-bit Up/Down Counter/Shift Register Introduction Description The AT6000 Series field programmable gate array FPGA lets the designer implement a synchronous, 16-bit Up/Down Counter/Shift Register that operates at 22 MHz under the worst commercial operating conditions. In this


    Original     		16-bit AT6000 16-bit AT6005 0465C 09/99/xM 74194 shift register 74194 74193 shift register ttl 74194 logic diagram 74193 74194 function table half-adder by using D flip-flop 74193 counter data sheet Asynchronous up and down counter 74194 datasheet PDF

    74194 shift register

    Abstract: 74377 register logicaps shift register by using D flip-flop 7474 74191 counter 74377 Latches 74373 altera logicaps TTL library 74374 74373 ttl 74191
    Text: €Pßl400 PROGRAMMABLE BUS PERIPHERAL FEATURES GENERAL DESCRIPTION • Bus I/O —Register Intensive Buster EPLD The EPB1400 (Buster) EPLD from Altera repre­ sents the firs t M icro proce ssor Peripheral UserConfigurable at the Silicon level. The device consists


    OCR Scan     		25MHz EPB1400 EPB1400 74194 shift register 74377 register logicaps shift register by using D flip-flop 7474 74191 counter 74377 Latches 74373 altera logicaps TTL library 74374 74373 ttl 74191 PDF

    TTL 74139

    Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
    Text: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at


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    74169 SYNCHRONOUS 4-BIT BINARY COUNTER

    Abstract: 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 bcd counter using j-k flip flop diagram Multiplexer 74153 CI 74138
    Text: AUGUST 1984 semiconductor MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION FEATURES The OKI MSM60300, MSM60700, and MSM61000 gate arrays are fabricated using state-of-the-art 3/i dual-layer metal silicon gate CMOS technology. A unit cell consists of 4 pairs o f transistors


    OCR Scan     		MSM60300, MSM60700, MSM61000 MSM61000 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 bcd counter using j-k flip flop diagram Multiplexer 74153 CI 74138 PDF

    truth table for ic 74138

    Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
    Text: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture


    OCR Scan     		44-Mbyte, 386-based truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table PDF

    74191, 74192, 74193 circuit diagram

    Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
    Text: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and


    OCR Scan     		HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411 PDF

    7486 XOR gate

    Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
    Text: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­


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    74299 universal shift register

    Abstract: 0x80808080 "shift register" alu
    Text: PSoC Creator Component Data Sheet Shift Register ShiftReg 1.50 Features • Adjustable shift register size: 2 to 32 bits • Simultaneous shift in and shift out • Right shift or left shift • Reset input forces shift register to all 0s • Shift register value readable by CPU or DMA


    Original     		74xxx 74299 universal shift register 0x80808080 "shift register" alu PDF

    sn 74373

    Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
    Text: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher


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    74194 logic diagram

    Abstract: 74165 parallel to serial 74194 function table
    Text: PSoC Creator Component Datasheet Shift Register ShiftReg 2.10 Features • Adjustable shift register size: 2 to 32 bits • Simultaneous shift in and shift out  Right shift or left shift  Reset input forces shift register to all 0s  Shift register value readable by CPU or DMA


    Original     		74xxx 74194 logic diagram 74165 parallel to serial 74194 function table PDF

    7474 D flip-flop

    Abstract: vhdl code for 74154 4-to-16 decoder 7478 J-K Flip-Flop vhdl code for 74194 74138 full subtractor 3-8 decoder 74138 shift register by using D flip-flop 7474 full subtractor circuit using xor and nand gates vhdl code for 8-bit BCD adder 74823 FULL ADDER
    Text: Chapter 3 - Macro Library Reference Chapter 3: The Macro Library The QuickLogic Macro Library contains over 500 macros and macro building blocks. While these macros offer a wide range of functions and flexibility, they fall into familiar functional groups. The naming conventions employed in the library are easy


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    full subtractor circuit using xor and nand gates

    Abstract: 74138 full subtractor 3-input-XOR 74138 decoder 7474 D flip-flop vhdl code for 8-bit BCD adder data sheet 74139 vhdl code for 8 bit ODD parity generator 74171 74594
    Text: Chapter 10 - Macro Library Reference Chapter 10: The Macro Library The QuickLogic Macro Library contains over 475 macros and macro building blocks. While these macros offer a wide range of functions and flexibility, they fall into familiar functional groups. The naming conventions employed in the library are easy


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    up down counter using IC 7476

    Abstract: full adder using Multiplexer IC 74151 74154 shift register IC sk 7443 full adder circuit using ic 74153 multiplexer DN 74352 full adder using ic 74138 74183 adder pin function of ic 74390 7478 J-K Flip-Flop
    Text: FUJITSU MICROELECTRONICS FUJITSU 37417bH 0010SÔ3 23E D MB65XXXX MB66XXXX MB67XXXX AV CMOS SERÍES GATE ARRAYS ~ June 1986 Edition 2.0 : T - 4 2 - n - o °i DESCRIPTION S The Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to provide high


    OCR Scan     		37417bH 0010S MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx MB65xxxx) MB67xxxx) 350AVB S40AVB up down counter using IC 7476 full adder using Multiplexer IC 74151 74154 shift register IC sk 7443 full adder circuit using ic 74153 multiplexer DN 74352 full adder using ic 74138 74183 adder pin function of ic 74390 7478 J-K Flip-Flop PDF

    74299 universal shift register

    Abstract: 74597 74XXX
    Text: PSoC Creator Component Data Sheet Shift Register ShiftReg 1.60 Features • Adjustable shift register size: 2 to 32 bits • Simultaneous shift in and shift out • Right shift or left shift • Reset input forces shift register to all 0s • Shift register value readable by CPU or DMA


    Original     		74xxx 74299 universal shift register 74597 PDF

    7408, 7404, 7486, 7432 use NAND gate

    Abstract: JLCC-68 ci 74386 cI 74150 jLCC68 74153 full adder 7402, 7404, 7408, 7432, 7400 74106 sln 7404 LCC-64
    Text: MB65XXXX MB66XXXX MB67XXXX AV CMOS SERIES GATE ARRAYS F U JIT S U June 1986 Edition 2.0 DESCRIPTION The Fujitsu MB65xxxx/M B66xxxx/M B67xxxx family are a series o f high perform ance CMOS gate arrays designed to provide high density, low pow er, and operating speeds th a t are com parable to standard bipolar logic. The A V M 865xxxx series is an ideal


    OCR Scan     		MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx M865xxxx) MB67xxxx) MB66xxxx) 350AVB 540AVB 850AVB 7408, 7404, 7486, 7432 use NAND gate JLCC-68 ci 74386 cI 74150 jLCC68 74153 full adder 7402, 7404, 7408, 7432, 7400 74106 sln 7404 LCC-64 PDF

    74194 internal circuit diagram

    Abstract: No abstract text available
    Text: PSoC Creator Component Datasheet Shift Register ShiftReg 2.0 Features • Adjustable shift register size: 2 to 32 bits • Simultaneous shift in and shift out  Right shift or left shift  Reset input forces shift register to all 0s  Shift register value readable by CPU or DMA


    Original     		74xxx 74194 internal circuit diagram PDF

    IC 3-8 decoder 74138 pin diagram

    Abstract: full adder using ic 74138 full adder using Multiplexer IC 74151 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 DN 74352 circuit diagram for IC 7483 full adder application of ic 74153 ic 74148 block diagram 74191, 74192, 74193 circuit diagram
    Text: MB65XXXX MB66XXXX MB67XXXX AV CMOS SERIES GATE ARRAYS F U JIT S U June 1986 Edition 1.0 DESCRIPTION The Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to provide high density, low power, and operating speeds that are comparable to standard bipolar logic. The AV MB65xxxx series is an ideal


    OCR Scan     		MB65XXXX MB66XXXX MB67XXXX MB65xxxx/MB66xxxx/MB67xxxx MB65xxxx) MB67xxxx) MB66xxxx) IC 3-8 decoder 74138 pin diagram full adder using ic 74138 full adder using Multiplexer IC 74151 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 DN 74352 circuit diagram for IC 7483 full adder application of ic 74153 ic 74148 block diagram 74191, 74192, 74193 circuit diagram PDF

    IC 3-8 decoder 74138 pin diagram

    Abstract: binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 ic 74148 block diagram MSI IC 74138 decoder
    Text: s I SEMICONDUCTOR GROUP 23E D • t?54E40 G00fl535 1 "T-q2-q \ p a rtII CMOS STANDARD CELL LSI MSM91H000 SERIES ¿U S' This M a terial C o p y r i g h t e d B y Its R e s p e c t i v e M a n u f a c t u r e r O K I SEMICONDUCTOR GROUP 23E D ■ b72M240 DGGÔ23b G


    OCR Scan     		MSM91H000 b72MS40 DQQ023b t-42-41 b724240 IC 3-8 decoder 74138 pin diagram binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 ic 74148 block diagram MSI IC 74138 decoder PDF

    ALU IC 74381

    Abstract: encoder IC 74147 16CUDSLR 74139 truth table alu 74382 truth table for 7446 from ic 7447 truth table IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
    Text: PLDS-HPS, PLS-HPS, PLS-OS & PLS-ES A N & * r a \ MAX+PLUS II Programmable Logic Development System & Software Data Sheet S eptem ber 1991, ver. 1 U M A X + P L U S II is the single, u nified d e velo p m e n t system for A lte ra 's C lassic, M A X 5000, M A X 7000, and S T G E P L D s .


    OCR Scan     		486-based 12-ms 44-Mbyte, ALU IC 74381 encoder IC 74147 16CUDSLR 74139 truth table alu 74382 truth table for 7446 from ic 7447 truth table IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138 PDF