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    Untitled

    Abstract: No abstract text available
    Text: MIT SUB ISHI íDGTL LOGIC} 11 91D Í>É| baM'iñS? 0 0 1 2 1 7 4 12174 D , o^ oO ° V itS N 2 T lY iiis u B is m ^ S T T L s M 74AS00P r T = V 3 -/S " QUADRUPLE 2-INPU T POSITIVE NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The 74AS00P is a semiconductor integrated circuit


    OCR Scan     		PDF 74AS00P M74AS00P DD1S17J 20-PIN 24P4D 24-PIN

    Untitled

    Abstract: No abstract text available
    Text: M ITSUBISHI A S T T L s M 74A S00P QUADRUPLE 2 -INPUT POSITIVE NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW Th e M 74A S 00P is a sem iconductor integrated circuit consisting of four 2-input positive-logic N A N D gates, us­ ab le as negative-log ic N O R gates.


    OCR Scan     		PDF