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Rochester Electronics LLC 74F109SJ IC FF JK TYPE DUAL 1BIT 16SOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74F109SJ	Tube			1,402	1 - 10 - 100 - 1000 - 10000 $0.21	Buy Now
onsemi 74F109SJX IC FF JK TYPE DUAL 1BIT 16SOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74F109SJX	Reel			2,000	1 - 10 - 100 - 1000 - 10000 $0.375	Buy Now
Rochester Electronics LLC 74F109SJX IC FF JK TYPE DUAL 1BIT 16SOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74F109SJX	Bulk			1,402	1 - 10 - 100 - 1000 - 10000 $0.21	Buy Now
Fairchild Semiconductor Corporation 74F109SJ J-Kbar Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16 '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	74F109SJ		6,627		1	1 $0.2058 10 $0.2058 100 $0.1935 1000 $0.1749 10000 $0.1749	Buy Now
Fairchild Semiconductor Corporation 74F109SJX J-Kbar Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16 '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	74F109SJX		5,702		1	1 $0.2058 10 $0.2058 100 $0.1935 1000 $0.1749 10000 $0.1749	Buy Now

74F109SJ Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74F109SJ		Fairchild Semiconductor	Dual JK Positive Edge-Triggered Flip-Flop		Original	PDF
74F109SJ		National Semiconductor	Dual J Inverted K Positive Edge-Triggered Flip-Flop		Original	PDF
74F109SJC		National Semiconductor	Dual JInvertedK Positive Edge-Triggered Flip-Flop		Original	PDF
74F109SJCX		National Semiconductor	Dual JInvertedK Positive Edge-Triggered Flip-Flop		Original	PDF
74F109SJX		Fairchild Semiconductor	Dual JK# Positive Edge-Triggered Flip-Flop		Original	PDF
74F109SJX		Fairchild Semiconductor	Dual JK Positive Edge-Triggered Flip-Flop		Original	PDF

74F109SJ Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
74F109 Abstract: 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A Text: 54F 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed completely independent transition clocked JK flip-flops The clocking operation is independent of rise and fall times of the clock waveform The JK design allows operation as a D flip-flop refer to ’F74	Original	74F109 74F109PC 16-Lead 20-3A 74F109 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A	PDF
54F109DM Abstract: 54F109FM 54F109LM 74F109PC F109 J16A M16A M16D N16E 74F109 Text: LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation	Original	74F109PC 16-Lead 16-Lead ds009471 54F109DM 54F109FM 54F109LM 74F109PC F109 J16A M16A M16D N16E 74F109	PDF
74F109 Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E Text: Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.	Original	74F109 74F109SC 16-Lead MS-012, 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E	PDF
74F109 Abstract: F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild Text: Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.	Original	74F109 74F109SC 16-Lead MS-012, 74F109 F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild	PDF
74F109 Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E Text: Revised January 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to CD sets Q to LOW level The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.	Original	74F109 74F109SC 16-Lead MS-012, 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E	PDF
74F109 Abstract: No abstract text available Text: 54F109,74F109 Dual JK Note: Overbar Over the K Positive Edge-Triggered Flip-Flop Literature Number: SNOS149A LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH General Description	Original	54F109 74F109 SNOS149A 54F/74F109 54F/74F109 74F109	PDF
74F109 Abstract: No abstract text available Text: LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation	Original	54F/74F109 54F/74F109 74F109PC 74F109SC 74F109SJ ds009471 74F109	PDF
a215c Abstract: 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E Text: A p riM 9 8 8 Revised January 1999 74F109^ Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to Cp sets Q to LOW level T he F 1 09 consists of tw o high-speed, com pletely indepen dent transition clocked JK flip-flops. The clocking operation	OCR Scan	74F109^ a215c 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E	PDF
74F109 Abstract: No abstract text available Text: *p n l1 9 , æ Revised January 1999 SEMICONDUCTOR TM 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q sets Q to LOW level The F109 consists of tw o high-speed, com pletely indepen den t transition clocked JK flip-flops. The clocking operation	OCR Scan	74F109 74F109SC 74F109SJ 74F109PC	PDF
Untitled Abstract: No abstract text available Text: tß National Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The 'F109 consists of two high-speed, completely indepen dent transition clocked JR flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.	OCR Scan	54F/74F109 74F109PC 54F109DM 74F109SC 74F109SJ	PDF
fan 7320 Abstract: fairchild fan 7320 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 Text: A p n i1 9 8 8 jgmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm ReVISed N OVem D6T 1 99 9 S E M IC O N D U C T O R TM 74F109_ Dual JK Positive Edge-Triggered Flip-Flop General Description A s y n c h ro n o u s In p u ts : T h e F 1 0 9 c o n s is ts o f tw o _ h ig h -s p e e d , c o m p le te ly in d e p e n	OCR Scan	74F109_ 74F109SC 16-Lead fan 7320 fairchild fan 7320 74F109 74F109PC 74F109SJ F109 M16A M16D MS-001	PDF
74F109 Abstract: No abstract text available Text: & November 1994 Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely indepen dent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.	OCR Scan	54F/74F109 74F109PC 20-3A 74F109	PDF
L02 pin Abstract: 74F109 Text: g & National Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The 'F109 consists of two high-speed, completely indepen dent transition clocked JR flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.	OCR Scan	54F/74F109 74F109PC 54F109DM 74F109SC 74F109SJ DQ62213 L02 pin 74F109	PDF