74LSOO

Contextual Info: H D 74LS21. Dual 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item T a = - 20~ + 75°C) min T e s t Conditions Symbol ‘yp* max Unit VlH 2 .0 - - V VlL - - 0 .8 V V Input voltage VOH Vcc = 4.75V , Vih = 2V, Ioh = —400/iA

Contextual Info: 54/7421 54H/74H21 54LS/74LS21 ORDERING CODE PIN CONFIGURATIONS See Section 9 for further Package and Ordering Information. PACKAGES PIN CONF. COMMERCIAL RANGES MILITARY RANGES VCC = 5V ± 5%; Ta = 0°C to *70°C VCC = 5V ± 10"/.; Ta = -55°C to *125°C

7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Contextual Info: Signehcs I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 8mA 74S20 3ns 7421 12ns 8mA 74LS21

TTL 7421

Abstract: 7421 ttl AND gate TTL 7420 74LS21 PIN CONFIGURATION 7421 pin configuration 7420 pin configuration 74LS gates 7420 nand 74ls gate symbols PIN CONFIGURATION 7420
Contextual Info: Signetics I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3ns 8mA 7421 12ns 8mA 74LS21

TTL 7421

Abstract: 7421 ttl AND gate 7421 pin configuration PIN CONFIGURATION 7420 TTL 7420 logic gate 7421 AND 74LS20 PIN CONFIGURATION 7420 pin configuration 7420 SIGNETICS TTL 74LS20
Contextual Info: 7420, 7421, LS20, LS21, S20 Signetics Gates Dual Four-Input NAND 20 AND (’21) Gate Product Specification Logic Products TYPE TYPICAL SUPPLY CURRENT (TOTAL) TYPICAL PROPAGATION DELAY 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3 ns 8mA 7421 12ns 8mA 74LS21 9ns

ic 7421

Abstract: TTL 7421 7421 ttl AND gate IC 7420 pin configuration ic 7421 function ic 7421 TTL 7420 7421 IC ic ttl 7421 pin configuration ic 7420
Contextual Info: Signetics I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification H TYPICAL SUPPLY CURRENT (TOTAL) TYPICAL PROPAGATION DELAY TYPE 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3ns 8mA 7421 12ns 8mA 74LS21

TTL 74ls21

Abstract: 751A-02 motorola 74ls21
Contextual Info: SN54/74LS21 DUAL 4-INPUT AND GATE DUAL 4-INPUT AND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

74LS21

Abstract: 7421 pin configuration 74LS N7421F N7421N N74H21F N74H21N N74LS21F N74LS21N S5421F
Contextual Info: 54/7421 54H/74H21 54LS/74LS21 ORDERING CODE PIN CONFIGURATIONS See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES = 5V ± 5%; T a = 0°C to *70°C PACKAGES PIN CON F. Plastic DIP Fig. A Fig. A N7421N • N74H21N N74LS21N

74LS21 PIN CONFIGURATION

Abstract: 74LS21 54LS 74LS
Contextual Info: GD54/74LS21 DUAL 4-INPUT POSITIVE AND GATES Description Pin Configuration This device contains two independent 4-input AND gates. It performs the Boolean functions Y = A B C D or Y = A + B + C + D in positive logic. V Cc 2D 2C NC 2B 2A 2Y 1A 1B NC 1C 1D 1Y

ls 7421

Abstract: logic gate 7421 AND 74LS21
Contextual Info: NATIONA L S E M C O N D {LOGIC} DEE D I LSQ115E DD^bSt, 1 I 21 T -< /3 -/!T CONNECTION DIAGRAMS PINOUT A 54/7421 54H/74H21 54LS/74LS21 DUAL 4-INPUT POSITIVE AND GATE ORDERING COPE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, = 0°C to +70° C

74LS21

Abstract: TTL 74ls21 sn54/74ls21 751A-02
Contextual Info: SN54/74LS21 DUAL 4-INPUT AND GATE DUAL 4-INPUT AND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

7421 AND gate

Abstract: 7421 74LS21 74LS21P 7421 Dual 4-input AND gate 74LS21PC 74LS21DC DC5421 54H21DM 54H21FM
Contextual Info: 21 CO NNECTIO N DIAGRAMS PINOUT A /5 4 /7 4 2 1 i/54H/74H21 r 54LS/74LS21 / m s t - ^ fo f/c a DUAL 4-IN P U T POSITIVE AND GATE ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V +10%,

74ls21 IC

Contextual Info: SANYO SEMICONDUCTOR CORP I EE D LC74HC21 PU 1 im a n n DQoat .33 a CMOS High-Speed Standard Logic LC74HC Series 3003a Dual 4-Input AND Gate E 1743C Features • The LC74HC21 consists of 2 identical 4-input AND gates. • Uses CMOS silicon gate process technology to achieve operating speeds similar to L S -T T L (74LS21 with the

74ls21p

Abstract: 7421 Dual 4-input AND gate 74LS21 74H21 7421 54H21DM 54H21FM 54LS21 54LS21FM 74LS21PC
Contextual Info: 21 C O N N E C T IO N D IA G R A M S P IN O U T A /5 4 /7 4 2 1 54H /74H 21 r / ^54LS/74LS21 ^^ DUAL 4-IN P U T POSITIVE AND GATE O R D E R IN G CO D E: See S e ctio n 9 PIN PKGS OUT C O M M E R C IA L G RADE M ILITA R Y G RADE V c c = + 5.0 V ±5%, T a = 0 °C to + 7 0 ° C

logic diagram of 7432

Abstract: CI 7408 TTL 7486 7408 s.i 7408 FL 9014 7486 nor CI 74LS08 7408 fairchild 7432 TTL
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn

Contextual Info: SGS-THOMSON *JÆURjflDÊIMJllILiÊTrmDÊi M54HC21 M74HC21 DUAL 4-INPUT AND GATE • HIGH SPEED tpD = 11 ns TYP. at VCc = 5V ■ LOW POWER DISSIPATION Icc = 1 #iA (MAX.) at Ta = 25°C ■ HIGH NOISE IMMUNITY V nih = VN|L = 28“/ o VCC (MIN.) ■ OUTPUT DRIVE CAPABILITY

Contextual Info: TYPES SN54H21, SN54LS21, SN74H21, SN74LS21 DUAL 4-INPUT P0SIT1VE-AND GATES _ REVISED APRIL 1985 SN54H21 . . . JPACKAGE SN54LS21 . . . J OR W PACKAGE S N 74H 21 . . . J OR N PACKAGE SN74LS21 . . . D, J OR N PACKAGE • * Package Options include Both Plastic and

74hc21

Contextual Info: M54HC21 M74HC21 Æ 7 SCS-THOM SON Ä 7#„ RHD glSÌ IIL[l(§ì[n!©li8B(gS DUAL 4-INPUT AND GATE • HIGH SPEED tPD = 11 ns (TYP. at VCc = 5V ■ LOW POWER DISSIPATION ICC = 1 /»A (MAX.) at Ta = 25°C ■ HIGH NOISE IMMUNITY V n IH = V nil = 28% Vcc (MIN.)

Contextual Info: TYPES SN74LS21, SN54LS21 DUAL 4-INPUT POSITIVE-AND GATES R E V IS E D A P R IL 1985 • Package Options Include Standard Plastic N and Ceram ic (J) 300-mil D ual-In-Line Pa ckage s, P la stic Sm all Outline (D) and Ceramic Chip Carrier <FK) Package • Dependable Texas Instruments Quality and

Contextual Info: SbE D • 7 ^ 2 3 ? D 0 3 eJ 7 74 Û12 ■ S G T H r z z S C S -T H O M S O N M 54H C 21 ^ ■ 7 # . ¡ a ffim iC T E iM n ig s _ M 7 4 H C 2 1 S Q S - THOMSON 2 / DUAL 4-INPUT AND GATE ■ HIGH SPEED tpo = 11 ns TYP. at V c c = 5V ■ LOW POWER DISSIPATION

M54HC21

Abstract: M54HC21F1R M74HC21 M74HC21B1R M74HC21C1R M74HC21M1R
Contextual Info: M54HC21 M74HC21 DUAL 4-INPUT AND GATE . . . . . . . . HIGH SPEED tPD = 10 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28% VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

M54HC21

Abstract: M54HC21F1R M74HC21 M74HC21B1R M74HC21C1R M74HC21M1R
Contextual Info: M54HC21 M74HC21 DUAL 4-INPUT AND GATE . . . . . . . . HIGH SPEED tPD = 10 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28% VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

TTL 7486

Abstract: FL 9014 TTL 7421 ttl 7432 TTL 7411 TTL 7409 7486 TTL 7411 74LS86 74LS08
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi ly i r n

Contextual Info: r z 7 S C S -T H O M S O N Ä 7# M54HC21 M74HC21 DUAL 4-INPUT AND GATE HIGH SPEED tpD = 10 ns TYP. AT Vcc = 5 V LOW POWER DISSIPATION Ice = 1 nA (MAX.) AT Ta = 25 "C HIGH NOISE IMMUNITY Vnih = Vnil = 28% Vcc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTLLOADS SYMMETRICAL OUTPUT IMPEDANCE