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    Contextual Info: M m p n M 8 I 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, FLOW-THROUGH ZBT SRAM O lV ilU ^ IV IU MT55L128L18F, MT55L64L32F, MT55L64L36F ZBT SRAM 3.3V Vdd, 3.3V I/O FEATURES High frequency and 100 percent bus utilization Fast cycle times: 10ns, 11ns and 12ns Single +3.3V +5% power supply


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    MT55L128L18F, MT55L64L32F, MT55L64L36F 55L128L18F PDF

    Contextual Info: HM5216808C Series HM5216408C Series 1,048,576-word x 8-bit x 2-bank Synchronous Dynamic RAM SSTL-3 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM (SSTL-3) HITACHI ADE-203-617 (Z) Preliminary Rev. 0.0 Jul. 10, 1996 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216808C Series,


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    HM5216808C HM5216408C 576-word 152-word ADE-203-617 Hz/100 Hz/83 7777K\ PDF

    Contextual Info: HB526C264EN-10IN, HB526C464EN-10IN 1.048.576-word x 64-bit x 2-bank Synchronous Dynamic RAM Module 1.048.576-word x 64-bit x 4-bank Synchronous Dynamic RAM Module HITACHI ADE-203-737A Z Rev. 1.0 Feb. 7, 1997 Description The HB526C264EN, HB526C464EN belong to 8-byte DIMM (Dual In-line Memory Module) family,


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    HB526C264EN-10IN, HB526C464EN-10IN 576-word 64-bit ADE-203-737A HB526C264EN, HB526C464EN HB526C264EN PDF

    WD83C690

    Abstract: WD83B692 WD83C691
    Contextual Info: WD83C690 DESCRIPTION AND APPLICATION 1.0 DESCRIPTION AND APPLICATION The WD83C690 Ethernet LAN Controller ELC is a VLSI device designed to interface with networks such as Ethernet, Cheapernet, and StarLAN. Functionally similar to the National DP8390 device,


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    WD83C690 WD83C690 --------------------------------------T54 -T63--------------- 75VVDD WD83B692 WD83C691 PDF

    R40 AH

    Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are


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    HM5283206 072-word 32-bit ADE-203-223A Hz/83 Hz/66 z//77////////a QQ27flfl2 R40 AH PDF

    HM5241

    Abstract: HM5241605CTT15
    Contextual Info: HM5241605C Series Preliminary 131,072-w ord x 16-bit x 2-bank Synchronous Dynam ic RAM H IT A C A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance. Features • 3.3 V Power supply


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    HM5241605C 072-w 16-bit 400-mil 50-pin CP-50D) TTP-50D) HM5241 HM5241605CTT15 PDF

    rft electronica

    Contextual Info: HM52161 65 Series Preliminary 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs arc referred to the rising edge of the clock input. The H M 5 2 16165 is offered in 2 banks for improved performance. Features Rev. 0.0 Jul. 2 9 ,1 9 9 4


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    HM52161 288-word 16-bit HM5216165TT-10 HM5216165TT-12 HM52161657T-15 400-mii 50-pin TTP-50D) Hz/83 rft electronica PDF

    Contextual Info: HM5221605 Series Preliminary 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clo ck input. The HM5221605 is offered in 2 banks for improved performance. Features Rev. 0.1 Sep. 22,1994


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    HM5221605 536-word 16-bit HM5221605TT-20 HM5221605TT-17 HM5221605TT-15 400-mil 50-pin TTP-50DA) PDF

    Contextual Info: M O SEL VETEUC V52C4256 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM HIGH PERFORMANCE V52C4256 60 70 80 10 Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns 100 ns Max. CAS Access Time, (tCAC) 15 ns 20 ns 25 ns 25 ns Max. Column Address Access Time, (1M )


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    V52C4256 V52C4256 GG030bS PDF

    CHN 920

    Abstract: CHN 628 9426 circuit diagram of plcc modem CT31 NS16450 NS16C552 NS16C552V
    Contextual Info: NS16C552 yw\National JimSemiconductor NS16C552 Dual Universal Asynchronous Receiver/Transmitter with FIFOst General Description F e a tu re s The NS16C552 is a dual version of the NS16550AF Univer­ sal Asynchronous Receiver/Transmitter UART . The two serial channels are completely independent except for a


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    NS16C552 NS16550AF NS16450* NSt6C552XX tl/c/9426-20 CHN 920 CHN 628 9426 circuit diagram of plcc modem CT31 NS16450 NS16C552V PDF

    v52c4258

    Contextual Info: M O S E L VTTEUC V52C4258 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM HIGH PERFORMANCE V52C4258 Max. RAS Access Time, I rac 60 70 80 10 60 ns 70 ns 80 ns 100 ns 25 ns Max. CAS Access Time, Ocac ) 15 ns 20 ns 25 ns Max. Column Address Access Time, Paa )


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    V52C4258 V52C4258 PDF

    MT58LC32K36C4

    Contextual Info: MT58LC32K36C4 32 KX 36 SYNCBURST SRAM |u iic :n o N 32K x 36 SRAM I +3.3V SUPPLY, PIPELINED AND SELECTABLE BURST MODE FEATURES • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View Fast access tim es: 4.5, 5, 6, 7 and 8ns


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    MT58LC32K36C4 128ns. PDF

    n5295

    Contextual Info: MN5295 MN5296 y M IC R O N E T W O R K S 17/isec, 16-Bit EXTENDED TEMPERATURE A/D CONVERTERS m b DESCRIPTION FEATURES High resolution, high speed, small package and the ability to operate over extended temperatures including -5 5 °C to + 125°C are brought together in the MN5295 and MN5296.


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    MN5295 MN5296 17/isec, 16-Bit 17/isec 14-Bit 32-Pin MIL-STD-1772 n5295 PDF

    Contextual Info: 19-0448; Rev 0, 11/95 A lilX IA I S e ria lly C o n tro lle d , L o w -V o lta g e , 8 -C h a n n e l S P S T S w itc h _General Description These CMOS devices can operate continuously with dual power supplies ranging from ±2.7V to ±8V or a single supply between +2.7V and +16V. Each switch


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    MAX395 MAX391 MAX335. 567bbSl 0013b73 PDF

    Contextual Info: HM5241605C Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-381B Z Rev. 2.0 Jan. 7, 1997 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance.


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    HM5241605C 072-word 16-bit ADE-203-381B Hz/57 /////////////77777k fr7//77/y///y77 PDF

    ACCM 5 pin

    Contextual Info: ADE-203-304 C (Z) HM5216805 Series HM5216405 Series 1048576-word x 8-bit x 2-bank Synchronous Dynamic RAM 2097152-word x 4-bit x 2-bank Synchronous Dynamic RAM Prelim inary HITACHI A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216805 Series,


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    ADE-203-304 HM5216805 HM5216405 1048576-word 2097152-word HM5216805TT-10 HM5216805TT-12 HM5216B05TT-15 ACCM 5 pin PDF

    Contextual Info: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-280A Z Rev. 1.0 Dec. 20, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.


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    HM5216165 288-word 16-bit ADE-203-280A Hz/83 Hz/66 PDF

    Contextual Info: MOSEL' VITELIC V53C8512/V53C9512 HIGH PERFORMANCE, LO W POWER 512K x 8 AND 5 1 2 K x 9 B IT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE V53C8512/V53C9512 PRELIMINARY 50/50L 60/60L 70/70L Max. RAS Access Time, tflAC 50 ns 60 ns 70 ns Max. Column Address Access Time, (ïcaa)


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    V53C8512/V53C9512 V53C8512/V53C9512 50/50L 110ns 60/60L 70/70L V53C8512L/V53C9512L V53C8512/9512 V53C8512/9512 PDF

    TE 109-27

    Contextual Info: Catalog 1307515 Issued 9-99 M IC T O R Connectors Prod uct Facts a 76 dedicated signal lines per linear inch B Surface mount family designed for parallel board-to-board, flex-toboard and cable-to-board configurations B Right-angle versions are available B 0.64 [.025] centerline


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    50-ohm r/7///7/77777777Ì 1/////77777777/A Z77/Zk K777//7777/77777k IV7/7/777777777A Y777/77777777777 Y/777/77/7/ 777/A TE 109-27 PDF

    MN373

    Abstract: Micro Networks mn373
    Contextual Info: mCtwo=.= MN5284 Series MICRO NETWORKS LOW-POWER 16-Bit A/D C ONVERTERS DESCRIPTION • 16-Bit Resolution • 15-Bit No Missing Codes • 300mW Max Power Consumption • 50/tsec Max Conversion Time • Serial and Parallel Outputs • True-TTL and 5V-CMOS Compatible


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    MN5284 16-Bit 15-Bit 300mW 50/tsec 32-Pin 50/isec MN373 Micro Networks mn373 PDF

    M5216

    Contextual Info: ADE-203-304 B (Z) HM5216805 Series HM5216405 Series 1048576-word x 8-bit x 2-bank Synchronous Dynamic RAM 2097152-word x 4-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising Aug. 4, 1995 Ordering Information edge of the clock input. The HM 5216805 Series,


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    ADE-203-304 HM5216805 HM5216405 1048576-word 2097152-word HM5216805TT-10 HM5216805TT-12 HM5216805TT-15 HM5216405TT-10 HM5216405TT-12 M5216 PDF

    Contextual Info: MN5284 Series M IC RO NETW ORKS LOW-POWER 16-Bit AID CONVERTERS • 16-Bit Resolution • 15-Bit No Missing Codes • 300mW Max Power Consumption • 50/;sec Max Conversion Time • Serial and Parallel Outputs • True-TTL and 5V-CMOS Compatible • Small 32-Pin SideBrazed DIP


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    MN5284 16-Bit 16-Bit 15-Bit 300mW 32-Pin 50/isec PDF

    W777

    Abstract: electronica ddr
    Contextual Info: H M 5 2 1 6 8 0 5 Preliminary S e r ie s 1,048,575-word x 8-bit x 2-bank Synchronous Dynamic RAM HITACHI All Inputs and outputs are referred to the rising edge of tbe clock input. The HM5216805 is offered in 2 banks for improved performance. Features •3J V Power supply


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    575-word HM5216805 HM5218805TT-10 HM52ieaonr-i2 HM5218B06TT-15 TTP-440E) Hz/83 Hz/66 695/DDR/MFM M19TD4S W777 electronica ddr PDF

    v52c4258

    Contextual Info: M O S E L V IT E U C V52C4258 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512X 4 SAM HIGH PERFORMANCE V52C4258 60 70 80 10 60 ns 70 ns 80 ns 100 ns Max. CAS Access Time, tcAc 15 ns 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t^ ) 30 ns 35 ns 40 ns


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    V52C4258 V52C4258 b3533Tl 000311b PDF