AS7C1024

Abstract: AL205 AS7C31024 IN317
Contextual Info: Hi gh Per for m an ce 128K 128 K x8 C M OS S R A M A S 7C1024 A S 7C31024 1288K ×8 CMOS S R A M 12 Features • Organization: 131,072 words × 8 bits • High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time • Low power consumption

AS7C512-20JC

Abstract: AS7C512-15PC VLN 2003 7C256 AS7C512
Contextual Info: AS7C512 5V 64K x8 CMOS SRAM 1Equal access and cycle tim es 1Easy m em ory expansion w ith CE1, CE2, OE inputs 1TTL-compatible, three-state I/O - 3 2-pin JEDEC standard packages - 300 m il PDIP and SOJ Socket com patible w ith 7C256 and 7C1024 1ESD p rotection > 2000 volts

7C1024

Contextual Info:  $6& 9.ð&02665$0 &RPPRQ,2 HDWXUHV • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024 - 8x13.4 TSOP • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA

Contextual Info: High Performance 128Kx8 C M O S SRAM p i 7C1024 7C1024L 128Kx8 CM O S S RAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE1, CE2, OE inputs - 10/12/15/20/25/35 ns address access time

Contextual Info: High Performance 32Kx8 CMOS SRAM p i AS7C256 AS7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits Equal access and cycle times • High speed Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time

7C1024

Abstract: AS7C256
Contextual Info: AS7C256 5V 32K •8 CMOS SRAAA /Common I OV Features • O rganization: 3 2 ,7 6 8 w ords X 8 bits • H igh speed - 1 0 /1 2 /1 5 / 2 0 ns address access tim e - 3 / 3 / 4 / 5 ns o utput enable access tim e • Low pow er consum ption - Active: 660 m W m ax 10 ns cycle

Contextual Info: H ig h P erfo rm a n ce 32K X8 CMOS SRAM AS7C.256 AS7C 256L A 32KX8 CMOS SRAM Common I/O • Organization: 32,768 words x 8 bits •H ig h sp eed - 1 0 /1 2 /1 5 /2 0 /2 5 /3 5 ns address access time - 3 / 3 / 4 / 5 / 6 /8 ns output enable access time • Low power consumption

Contextual Info: High Performance 128KX8 CMOS SRAM 7C1024 AS7C31024 128KX8 CMOS SRAM Features • Organization: 131,072 words x 8 bits • High speed - 1 0 / 1 2 / 1 5 / 2 0 / 2 5 ns address access time - 3 / 3 / 4 / 5 / 6 ns output enable access time • Low power consumption

CY7C1024AV33

Contextual Info: 024AV33 7C1024AV33 128K x 24 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE1, CE2, CE3 active and Write Enable (WE) inputs LOW. Data on the 24 I/O pins (I/O0 through I/O23) is then written into the location specified on the address pins (A0 through A16).

AS7C512-20JC

Abstract: AS7C512-15pc AS7C512 10n12 AS7C512-12JC 7C256 AS7C512L AS7CS12 Static Random Access Memory SRAM 7CS12-20
Contextual Info: High-Performance p i AS7C512 : AS7C512L CMOS SRAM 64Kx8 CMOS SRAM Common I/O FEATURES Organization; 65,536 words x 8 bits Equal access and cycle times High speed Easy memory expansion with CE1, CE2, OE inputs - 12/15/20/25/35 ns address access time TTL-compatible, three-state I/O

Collins Electronics

Abstract: lm 3751 AS7010 NT 407 F 0637 Z05 AS7C1024-20PC LR 3441 AS7C1024 AS7C31024 AS701024-12TJC
Contextual Info: H ig h P e r f o r m a n c e 128KX8 C M O S SR A M A 7C1024 AS7C31024 128KX8 CMOS SRAM Features • Organization: 131,072 words x 8 bits • High speed - 1 0 / 1 2 / 1 5 / 2 0 / 2 5 ns address access time - 3 / 3 / 4 / 5 / 6 n s output enable access time

Contextual Info: H igh P erform ance AS7C10 2 4 7C1024L 128KX8 CMOS SRAM A 128KX8 CMOS SRAM Features • O r g a n iz a tio n : 1 3 1 ,0 7 2 w o r d s x 8 b its • E asy m e m o r y e x p a n s i o n w i t h C E 1 , C E 2, O E in p u t s • H ig h s p e e d • T T L -c o m p a tib le , th r e e - s t a te I / O

MSM 6290

Abstract: msm 5562 27c256 intel 62c512 AP 2068 27C512 microchip 62256 57C256 27C512 SGS-THOMSON 27C512-150
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

TAA103

Contextual Info: 128Kx8 Fast SRAM A S 7 C I0 2 4 Features Logic Block Diagram ♦ High Performance CMOS: tAA=10-35 ns ♦ Fast OE access: t0 E= 3-8 ns ♦ Low power - 770 mW @ 100 MHz AO - 55 mW @ 10 MHz standby - A1 11 mW @10 MHz standby: L version A2 A3 ♦ 400-mil standard, 300-mil skinny pkgs

AS7C256

Abstract: 256x128x8 TI 344C
Contextual Info: High Performance 32Kx8 CMOS SRAM II ^ L lh . AS7C256 AS7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time

Contextual Info: H ig h P erfo r m a n c e 128Kx 8 CMOS SRAM « II AS7C 1024L 7C1024LL A Low power 1 2 8K X 8 CMOS SRAM C om m on I / O Advance information • Organization: 131,072 words x 8 bits • Single SV pow er supply • High speed - 5 5 /7 0 ns address access time

Contextual Info: AS7C512 5V 6 4K x8 C M O S SRAM Features • O rganization: 6 5 ,5 3 6 w ords X 8 bits • H igh speed - 1 5 /2 0 /2 5 ns address access tim e - 4 / 5 / 6 ns o utput enable access tim e • Low po w er consum ption - Active: 632 m W m ax 15 ns cycle - Standby: 27.5 m W max, CMOS I/O

Contextual Info: H igh P erfo rm a n ce •■ A S 7 C 1024 H 128Kx8 CMOS SRAM A S7C 31024 1 2 8 K X 8 C M O S SRAM C o m m o n I / O • O r g a n iz a tio n : 1 3 1 ,0 7 2 w o r d s x 8 b its • T T L /L V T T L -c o m p a tib le , th r e e - s ta te I / O • H ig h sp ee d

Contextual Info: H igh Perform ance 128KX8 CMOS SRAM AS 7C1 0 2 4 A S7C 31024 1 2 8 K X 8 C M O S SRAM Features • T T L /L V T T L -c o m p a tib le , th r e e - s ta te I / O • H ig h s p e e d • 3 2 - p i n JEDEC s ta n d a r d p a c k a g e s - 3 0 0 m il P D IP a n d SOJ

CY7C1024AV33

Contextual Info: 33 ADVANCE INFORMATION 7C1024AV33 128K x 24 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE1, CE2, CE3 active and Write Enable (WE) inputs LOW. Data on the 24 I/O pins (I/O0 through I/O 23) is then written into the location specified on the address pins (A0 through A16).

Contextual Info: CY7C101 CY7C102 ADVANCED INFORMATION CYPRESS _ SEMICONDUCTOR 262,144 x 4 Static R/W RAM with Separate I/O Features Functional Description • High speed T h e CY7C101 and C Y 7C I02 are high-perform ance C M O S static R A M s organized as 262,144 x 4 bits with separate I/O . Easy

27HC642

Abstract: 39C10B PAL22V10APC CY2254SC-1 7132SA70 93L422AM 7024S15 7130SA25 7C198-45C 7006S
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

AS7C256-20JC

Abstract: AS7C256 taa 723 7C256-10 7C256-12 7C256-15 AS7C256L AS7C256-15PC 7C1024
Contextual Info: High Performance 32Kx8 CMOS SRAM AS7C256 AS7C256L 32K×8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words × 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE and OE inputs – 10/12/15/20/25/35 ns address access time

CY7C1024AV33

Abstract: CY7C1024AV33-15AC
Contextual Info: 024AV33 7C1024AV33 128K x 24 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE1, CE2, CE3 active and Write Enable (WE) inputs LOW. Data on the 24 I/O pins (I/O0 through I/O23) is then written into the location specified on the address pins (A0 through A16).