8kx16bit ram
Abstract: 8kx16bit trz a7
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space
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8Kx16-BIT)
IDT71V218
256KB
10/12/15ns
48-pin
IDT71V218
200mV
71V218
SO48-1)
8kx16bit ram
8kx16bit
trz a7
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Untitled
Abstract: No abstract text available
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors :JÖi'Np Jdt) PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Common I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space
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8Kx16-BIT)
IDT71V218
256KB
48-pin
8Kx16
200mV
71V218
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PDF
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SE012
Abstract: 00000000ED SE012 diagram EM- 546
Text: UM5238 4-Bit Microcontroller with 32 Sec. Voice Synthesizer, LCD Driver and PSG Preliminary Features • ■ ■ ■ ■ m ■ ■ ■ ■ ■ ■ ■ 4-bit parallel processing ALU com patible w ith UM6610 8Kx16 bits program ROM bank switchable 128x 4 bits data RAM
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UM5238
UM6610
8Kx16
768KHz
122ns
SEG13
SEG12
SE012
00000000ED
SE012 diagram
EM- 546
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PDF
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TAG10_
Abstract: tag12 TAG13 8kx16bit
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space
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Original
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8Kx16-BIT)
IDT71V218
256KB
10/12/15ns
48-pin
IDT71V218
200mV
71V218
SO48-1)
TAG10_
tag12
TAG13
8kx16bit
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PDF
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TAG12
Abstract: TAG10_ tag13 8kx16bit cache tag Static RAM
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration – 14 Common I/O TAG Bits – 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space
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Original
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8Kx16-BIT)
IDT71V218
256KB
10/12/15ns
48-pin
IDT71V218
200mV
71V218
SO48-1)
TAG12
TAG10_
tag13
8kx16bit
cache tag Static RAM
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PDF
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Untitled
Abstract: No abstract text available
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Com m on I/O TA G Bits - 2 S eparate I/O Status Bits (VLD and D TY) • Optim ized for 256K B cache and 4G B cacheable space
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OCR Scan
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8Kx16-BIT)
IDT71V218
48-pin
IDT71V21B
8Kx16
4A25771
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PDF
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Untitled
Abstract: No abstract text available
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space
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OCR Scan
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8Kx16-BIT)
IDT71V218
256KB
48-pin
IDT71V2NOT
ro-we-2070
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PDF
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8kx16bit ram
Abstract: No abstract text available
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8 K x 16 C onfiguration - 14 Com m on I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • O ptim ized for 256KB cache and 4G B cacheable space
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OCR Scan
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3V128K
8Kx16-BIT)
IDT71V218
256KB
-10/12/15ns
48-pin
MO-118,
/15/W
727-fUÂ
8kx16bit ram
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PDF
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pin diagram of IC 74LS373
Abstract: No abstract text available
Text: M IC R O N MT56C0816 CACHE DATA SRAM DUAL 4Kx16 SRAM, SINGLE 8Kx16 SRAM CONFIGURABLE CACHE DATA SR A M FEATURES • O perates as two 4K x 16 SRAM s with common ad dresses and data; also configurable as a single 8K x 16 SRAM • Built-in input ad dress latches
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OCR Scan
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MT56C0816
4Kx16
8Kx16
52-Pin
MT56C
pin diagram of IC 74LS373
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PDF
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32Kx16
Abstract: AD73322 rom 8kx16 8kx16 870110
Text: COMMUNICATIONS: DSP SOLUTIONS MODEL MODEL Option On Chip Generic A/D or Codec On Chip DSP MIPS CYLCE TIME nsec CLK IN MHZ PROGRAM RAM ROM DATA RAM DMA PORTS HOST PORT TEMPERATURE Vcc RANGE +3.3V 0>70 -25/85 Smallest Package # Pins 2Kx24 PROGRAM RAM FLASH 8Kx24
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AD7729
ADSP2171
ADSP21MSP58
2Kx24
8Kx24
16Kx24
64Kbits
32Kx16
AD73322
rom 8kx16
8kx16
870110
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PDF
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ADSP210x
Abstract: LQFP100 16KX16 ADSP-210x 68-PGA 1kx16 ADSP-2186M
Text: DSP: 16 Fixed Point ADSP210x Based MODEL MODEL OPTION MIPS CYLCE TIME nsec PROGRAM RAM ROM DATA RAM CACHE SERIAL PORTS HOST PORT Vcc +3.3V TEMPERATURE RANGE -40 -55 +70 +85 +125 Smallest Package # Pins Price Reel /100’s Price (Reel) /100’s 68 PGA 68 PGA
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ADSP210x
ADSP2101
LQFP100
16KX16
ADSP-210x
68-PGA
1kx16
ADSP-2186M
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PDF
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1kx16
Abstract: 2Kx16 8Kx16 ADSP2101 ADSP2103 ADSP2104 ADSP2105 ADSP2109 ADSP2111 ADSP2115
Text: DIGITAL SIGNAL PROCESSING: FIXED POINT MODEL MODEL OPTION MIPS CYLCE TIME nsec PROGRAM RAM ROM DATA RAM CACHE SERIAL PORTS HOST PORT Vcc +3.3V TEMPERATURE RANGE 0>70 -25/85 # Pins -55/125 PRICE 100's General Purpose ADSP2101 40 10.24 ADSP2101 50 12.5 ADSP2101
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ADSP2101
ADSP2103
ADSP2104
ADSP2104L
ADSP2105
1kx16
2Kx16
8Kx16
ADSP2101
ADSP2103
ADSP2104
ADSP2105
ADSP2109
ADSP2111
ADSP2115
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PDF
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MS6132
Abstract: CM3K-67130 IDT7142SA45P CMS3-67130 CMRT MS6130-70PC 67140 CMSM-67005 67130 8kx16
Text: DPR MATRA MHS Dual Port RAM Cross Reference AMD AMD Part-Number AM2130-55PC AM2130-70PC TEMIC Part-Number CM3K-67130 L-55 CM3K-67130 L-55 Description 1Kx8 DPR MASTER PDIL48 55nsLP 1Kx8 DPR MASTER PDIL48 55nsLP TEMIC Part-Number CMSM-67005 L-35 CMSM-67005 L-45
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AM2130-55PC
AM2130-70PC
CM3K-67130
PDIL48
55nsLP
CMSM-67005
MS6132
IDT7142SA45P
CMS3-67130
CMRT
MS6130-70PC
67140
67130
8kx16
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PDF
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BT-308
Abstract: ADSP21062 2111 ram BB128 2164 RAM 2101 ram 1kx16 AD14060
Text: DSP and MIXED SIGNAL PROCESSORS MODEL MODEL MODEL MIPS CYLCE CLK TIME IN nsec MHZ PROGRAM RAM ROM DATA RAM CACHE SERIAL HOST PORTS PORT Vcc +3.3V TEMPERATURE RANGE 0>70 -25/85 -55/125 # Pins FIXED POINT Highest Performance: Concurrent Signal Processing ADSP
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21CSP01
21CSP11
21CSP11L
4Kx24
24Kx24
4Kx16
16Kx16
ADSP21062
BT-308
ADSP21062
2111 ram
BB128
2164 RAM
2101 ram
1kx16
AD14060
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PDF
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P-Channel Depletion-Mode
Abstract: MD80C31 JANTX2N4858 5962-9089101MEA SI9110AK JANTX2N6661 4Kx8 sram ttl MGM TRANSFORMER JANTX2N5114 janTXV2N5545
Text: Aerospace and Defense Product Offering Siliconix MIL–S–19500 Compliant Devices 2N5547JANTX MIL–S–19500/430 Siliconix Part No. Description 2N5547JANTXV MIL–S–19500/430 2N4856JAN MIL–S–19500/385 2N6660JANTX MIL–S–19500/547 2N4856JANTX MIL–S–19500/385
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2N5547JANTX
2N5547JANTXV
2N4856JAN
2N6660JANTX
2N4856JANTX
2N6660JANTXV
2N4856JANTXV
2N6661JAN
2N4857JAN
2N6661JANTX
P-Channel Depletion-Mode
MD80C31
JANTX2N4858
5962-9089101MEA
SI9110AK
JANTX2N6661
4Kx8 sram ttl
MGM TRANSFORMER
JANTX2N5114
janTXV2N5545
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PDF
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A12L
Abstract: IDT707278
Text: HIGH-SPEED 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS Integrated Device Technology, Inc. PRELIMINARY IDT707278S/L FEATURES: DESCRIPTION: • 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 8K x 16 banks - 512 Kilobit of memory on chip
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IDT707278S/L
16-bit
maDT707278S/L
100-pin
PN100-1)
512Kbit
A12L
IDT707278
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PDF
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A12L
Abstract: IDT70V7278
Text: HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS Integrated Device Technology, Inc. PRELIMINARY IDT70V7278S/L FEATURES: DESCRIPTION: • 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture — Four independent 8K x 16 banks
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IDT70V7278S/L
16-bit
x1DT70V7278S/L
100-pin
PN100-1)
70V7278
512Kbit
A12L
IDT70V7278
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PDF
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HPI mode interface in cy7c67300
Abstract: CYPRESS dual port sdram CY7C67300
Text: ADVANCE INFORMATION CY7C67300 CY7C67300 Embedded USB Host/Slave Controller Cypress Semiconductor Corporation Document #: 38-08015 Rev. * • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 13, 2002 ADVANCE INFORMATION CY7C67300
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CY7C67300
CY7C67300
HPI mode interface in cy7c67300
CYPRESS dual port sdram
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PDF
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8Kx16
Abstract: TA 8825 AN
Text: VLSI Technology , inc . ADVANCE INFORMATION VT62A168 • VT62A188 8K x18 OR TWO 4K x18 CACHE DATA SRAM FEATURES • High speed access times — Address access times of 25, 35, 45, 55 ns — A12 access direct mapped of 17, 25, 30 ns — Chip select access times of 20, 25,
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VT62A168
VT62A188
8Kx16
4Kx16
8Kx16
TA 8825 AN
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PDF
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CY7C67200
Abstract: 4KX16
Text: ADVANCE INFORMATION CY7C67200 CY7C67200 Mobile USB Host/Slave Controller Cypress Semiconductor Corporation Document #: 38-08014 Rev. * • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 13, 2002 ADVANCE INFORMATION CY7C67200
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CY7C67200
CY7C67200
4KX16
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PDF
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V727
Abstract: ce1111
Text: HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS I dt Integrated Device Technology, Inc. PRELIMINARY IDT70V7278S/L FEATURES: DESCRIPTION: • 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture — Four independent 8K x 16 banks
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OCR Scan
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IDT70V7278S/L
16-bit
IDT70V7278
100-pin
PN100-1
70V7278
512Kbit
V727
ce1111
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PDF
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A12L
Abstract: IDT707278
Text: HIGH-SPEED 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS Features ◆ ◆ ◆ ◆ ◆ ◆ 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture – Four independent 8K x 16 banks – 512 Kilobit of memory on chip Fast asynchronous address-to-data access time: 15ns
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16-bit
IDT707278S/L
p3/10/00:
200mV
A12L
IDT707278
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PDF
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O10L
Abstract: A12L IDT70V7278 "32K x 16" dual port SRAM O8L-15L
Text: HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS Integrated Device Technology, Inc. PRELIMINARY IDT70V7278S/L FEATURES: DESCRIPTION: • 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture — Four independent 8K x 16 banks
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Original
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IDT70V7278S/L
16-bit
x1IDT70V7278S/L
100-pin
PN100-1)
70V7278
512Kbit
O10L
A12L
IDT70V7278
"32K x 16" dual port SRAM
O8L-15L
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PDF
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A12L
Abstract: IDT707278 IDT707288 512kbit
Text: HIGH-SPEED 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS Integrated Device Technology, Inc. PRELIMINARY IDT707278S/L FEATURES: DESCRIPTION: • 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 8K x 16 banks - 512 Kilobit of memory on chip
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Original
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IDT707278S/L
16-bit
IDT707278
100-pin
PN100-1)
512Kbit
A12L
IDT707278
IDT707288
512kbit
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PDF
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