MC100EL92
Abstract: AN1560 EL90 SWITCH XCJC AN1503 DL140 LVEL11 LVEL16 motorola LOGIC
Text: AN1560 Application Note Low Voltage ECLinPS SPICE Modeling Kit Prepared by Cleon Petty Motorola Logic Applications Engineering ECLinPS and ECLinPS Lite are trademarks of Motorola, Inc. 6/97 Motorola, Inc. 1997 1 REV 1 AN1560 Low Voltage ECLinPS SPICE Modeling Kit
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AN1560
DL140
AN1560/D
MC100EL92
AN1560
EL90
SWITCH XCJC
AN1503
LVEL11
LVEL16
motorola LOGIC
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DK3200
Abstract: AGILENT H2000 DK3200 Evaluation Board lm339 pwm diagram Header 18X2 HP lcd connector 40 pin to 30 pin to 7 pin lm339 pwm EK51V720 AN1560 Header 13X2
Text: AN1560 APPLICATION NOTE Design Guide for the uPSD3200 Family The uPSD3200 family is a series of 8051-class microcontrollers MCUs containing an 8032 core with a large dual-bank Flash memory, a large SRAM, many peripherals, programmable logic, and JTAG In-System Programming (ISP) (see Figure 1.).
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AN1560
uPSD3200
8051-class
DK3200
uPSD3234A
80pin
AGILENT H2000
DK3200 Evaluation Board
lm339 pwm diagram
Header 18X2
HP lcd connector 40 pin to 30 pin to 7 pin
lm339 pwm
EK51V720
AN1560
Header 13X2
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K1213
Abstract: k1518 transistor c1213 equivalent transistor k1213 k1112 K1113 k0305 k0205 k0309 equivalent k1117
Text: AN1560/D Low Voltage ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora and Paul Shockman ON Semiconductor Broadband Application Engineers http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to extend the information given
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AN1560/D
AN1503
r14525
K1213
k1518
transistor c1213 equivalent
transistor k1213
k1112
K1113
k0305
k0205
k0309 equivalent
k1117
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k1213
Abstract: transistors k2628 transistor c1213 equivalent k1317 K0316 k2225 transistor k0232 k1117 k1518 k0317
Text: AN1560/D Low Voltage ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora and Paul Shockman ON Semiconductor Broadband Application Engineers http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to extend the information given
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AN1560/D
AN1503
r14525
AN1560/D
k1213
transistors k2628
transistor c1213 equivalent
k1317
K0316
k2225 transistor
k0232
k1117
k1518
k0317
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k2225 transistor
Abstract: k1118 k1117 k1213 power transistor k1821 transistor k1213 k1117 transistor K2225 k1518 transistor k1117
Text: AN1560/D Low Voltage ECLinPS and ECLinPS Lite SPICE Modeling Kit 150Prepared by Senad Lomigora and Paul Shockman ON Semiconductor Broadband Application Engineers http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to extend the information given
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AN1560/D
150Prepared
AN1503
k2225 transistor
k1118
k1117
k1213
power transistor k1821
transistor k1213
k1117 transistor
K2225
k1518
transistor k1117
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MOTOROLA 526
Abstract: EL90 AN1503 AN1560 DL140 LVEL11 LVEL16 MJE 521 LVPECL Q26 elite
Text: AN1560 Application Note Low Voltage ECLinPS SPICE Modeling Kit Prepared by Cleon Petty Motorola Logic Applications Engineering ECLinPS and ECLinPS Lite are trademarks of Motorola, Inc. 7/96 Motorola, Inc. 1996 5–1 REV 0 AN1560 Low Voltage ECLinPS SPICE Modeling Kit
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AN1560
AN1560/D*
AN1560/D
DL140
MOTOROLA 526
EL90
AN1503
AN1560
LVEL11
LVEL16
MJE 521
LVPECL
Q26 elite
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AN1560
Abstract: DK3200 abel i2c DK3200 Evaluation Board C51 Family uPSD3200 lm339 pwm speed 8032 intel AGILENT H2000 MON51
Text: AN1560 APPLICATION NOTE Design Guide µPSD3200 Family MPCONTENTS • µPSD3200 Family Overview ■ DK3200 Overview ■ DK3200 Development Board ■ Entering Design in PSDsoft Express ■ Watch it Run on DK3200 ■ Using uVision2 and ISD51 Debugger from Keil
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AN1560
PSD3200
DK3200
DK3200
ISD51
8051-class
AN1560
abel i2c
DK3200 Evaluation Board
C51 Family
uPSD3200
lm339 pwm speed
8032 intel
AGILENT H2000
MON51
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100EL91
Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
Text: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them
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MC100EL91
MC100EL91
MC100LVEL91.
r14525
MC100EL91/D
100EL91
MC100EL91DW
MC100EL91DWR2
MC100LVEL91
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AND8020
Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
Text: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL
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MC100EL90
MC100EL90
r14525
MC100EL90/D
AND8020
EL90
MC100EL90DW
MC100EL90DWR2
100EL90
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KPT25
Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Text: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal
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MC100EPT25
MC100EPT25
EPT25
r14525
MC100EPT25/D
KPT25
MC100EPT25D
MC100EPT25DR2
MC100EPT25DT
MC100EPT25DTR2
KA25
kpt25 alyw
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KVT23
Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
Text: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which
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MC100LVELT23
MC100LVELT23
LVELT23
MC100LVELT23/D
KVT23
MC100LVELT23D
MC100LVELT23DR2
MC100LVELT23DT
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MC100LVEL01
Abstract: MC100LVEL01D 1085 SPICE model
Text: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in
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MC100LVEL01
MC100LVEL01
LVEL01
KVL01
r14525
MC100LVEL01/D
MC100LVEL01D
1085 SPICE model
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KEL04
Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
Text: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those
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MC10EL04,
MC100EL04
MC10EL/100EL04
AND8003/D
r14525
MC10EL04/D
KEL04
HL04
HEL04
e104
MC100EL04
MC10EL04
HL-04
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MC100EL59
Abstract: MC100EL59DW MC100EL59DWR2 AND8020
Text: MC100EL59 5VĄECL Triple 2:1 Multiplexer The MC100EL59 is a triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random
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MC100EL59
MC100EL59
r14525
MC100EL59/D
MC100EL59DW
MC100EL59DWR2
AND8020
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EL12
Abstract: MC100LVEL12 MC100LVEL12D
Text: MC100LVEL12 3.3VĄECL Low Impedance Driver The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply.
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MC100LVEL12
MC100LVEL12
LVEL12
KVL12it
r14525
MC100LVEL12/D
EL12
MC100LVEL12D
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100EL56
Abstract: MC100EL56 MC100EL56DW MC100EL56DWR2
Text: MC100EL56 5V ECL Dual Differential 2:1 Multiplexer The MC100EL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals.
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MC100EL56
MC100EL56
MC100EL56/D
100EL56
MC100EL56DW
MC100EL56DWR2
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KVL33
Abstract: EL33 MC100LVEL33 MC100LVEL33D
Text: MC100LVEL33 3.3VĄECL ÷4 Divider The MC100LVEL33 is an integrated ÷4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the
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MC100LVEL33
MC100LVEL33
LVEL33
r14525
MC100LVEL33/D
KVL33
EL33
MC100LVEL33D
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LVE222
Abstract: MC100LVE222 MC100LVE222FA MC100LVE222FAR2 MB113
Text: MC100LVE222 3.3 V ECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single- ended with VBB output reference bypassed and connected to the
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MC100LVE222
MC100LVE222
LVE222
r14525
MC100LVE222/D
MC100LVE222FA
MC100LVE222FAR2
MB113
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HLT25
Abstract: MC10ELT25 ELT25 HT25 KLT25 MC100 MC100ELT25 TTL TRANSISTOR MODEL PARAMETER
Text: MC10ELT25, MC100ELT25 −5V Differential ECL to TTL Translator The MC10ELT/100ELT25 is a differential ECL to TTL translator. Because ECL levels are used, a +5 V, -5.2 V or -4.5 V and ground are required. The small outline 8-lead package and the single gate of
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MC10ELT25,
MC100ELT25
MC10ELT/100ELT25
ELT25
MC10ELT25/D
HLT25
MC10ELT25
HT25
KLT25
MC100
MC100ELT25
TTL TRANSISTOR MODEL PARAMETER
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E142 wafer format
Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Text: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001 SCILLC, 2001 Previous Edition 2000 “All Rights Reserved”
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DL140/D
Jan-2001
r14525
E142 wafer format
HEL32
MR 4710 IC
300w power amplifier circuit diagram
HEL05
klt22
HEL12 HEL31
HEL16
HLT22
HLT28
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w38 transistor
Abstract: LVE222 MC100LVE222
Text: MC100LVE222 3.3 V/5.0 V ECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single−ended with VBB output reference bypassed and connected to the
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MC100LVE222
MC100LVE222
LVE222
MC100LVE222/D
w38 transistor
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Untitled
Abstract: No abstract text available
Text: MC100LVE222 3.3 V/5.0 V ECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single-ended with VBB output reference bypassed and connected to the
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MC100LVE222
MC100LVE222
LVE222
MC100LVE222/D
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AN1404
Abstract: AND8020 MC100LVEL56 MC100LVEL56DW MC100LVEL56DWR2
Text: MC100LVEL56 3.3VĄECL Dual Differential 2:1 Multiplexer The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The device features both individual and common select inputs to
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MC100LVEL56
MC100LVEL56
r14525
MC100LVEL56/D
AN1404
AND8020
MC100LVEL56DW
MC100LVEL56DWR2
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EL33
Abstract: HEL33 KEL33 MC100EL33 MC10EL33 kl-33
Text: MC10EL33, MC100EL33 5VĄECL ÷4 Divider The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,
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MC10EL33,
MC100EL33
MC10EL/100EL33
r14525
MC10EL33/D
EL33
HEL33
KEL33
MC100EL33
MC10EL33
kl-33
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