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    AN549 Search Results

    AN549 Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    AN-549 Analog Devices New Features in the ADV601/ADV611 Original PDF
    AN-549 National Semiconductor Application Note 549 LM6361/LM6364/LM6365 Fast VIP Op Amps Offer High Speed at Low Power Consumption Original PDF
    AN549 STMicroelectronics THINNING DIGITAL PATTERNS USING THE IMSA110 Original PDF
    AN5491 Panasonic Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television Original PDF
    AN5491K Panasonic Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide TV Original PDF

    AN549 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    HC5502X

    Abstract: HC-5504X ptc overvoltage protections application note AN549 IB10 ballast schematic phillips HC-5504 telephone ring generator circuit telephone hybrid one chip RING GENERATOR
    Text: Wired Communications Application Notes Harris Semiconductor No. AN549.1 Harris Linear January 1997 The HC-5502X/4X Telephone Subscriber Line Interface Circuits SLIC Author: Geoff Phillips Introduction The HC-5502X/4X family of telephone subscriber line interface circuits (SLIC) integrate most of the BORSCHT functions


    Original     		PDF AN549 HC-5502X/4X HC-5502X/4X HC5502X HC-5504X ptc overvoltage protections application note IB10 ballast schematic phillips HC-5504 telephone ring generator circuit telephone hybrid one chip RING GENERATOR

    explain phase failure relay

    Abstract: No abstract text available
    Text: The HC-5502X/4X Telephone Subscriber Line Interface Circuits SLIC Application Note January 1997 AN549.1 Author: Geoff Phillips Introduction [ /Title () /Subject () /Autho r () /Keywords (Intersil Corporation, semiconductor, ) /Creator () /DOCI NFO pdfmark


    Original     		PDF HC-5502X/4X AN549 explain phase failure relay

    Untitled

    Abstract: No abstract text available
    Text: ICs for TV AN5491K Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television • Supports the multiple-point horizontal frequency 15.7 kHz to 62.7 kHz • Horizontal duty is controllable by external voltage.


    Original     		PDF AN5491K AN5491K

    EHT generation circuit diagram

    Abstract: TELEVISION EHT tv E.H.T circuit diagram CSB500F48 AN5491K horizontal output circuit with EHT TAFCSB500F48
    Text: ICs for TV AN5491K Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 • Supports the multiple-point horizontal frequency 15.7 kHz to 62.7 kHz


    Original     		PDF AN5491K EHT generation circuit diagram TELEVISION EHT tv E.H.T circuit diagram CSB500F48 AN5491K horizontal output circuit with EHT TAFCSB500F48

    AN549

    Abstract: IB10
    Text: The HC-5502X/4X Telephone Subscriber Line Interface Circuits SLIC TM Application Note January 1997 AN549.1 Author: Geoff Phillips Introduction employing either of the two single ended ringing methods and in balanced ringing systems. The HC-5502X/4X family of telephone subscriber line


    Original     		PDF HC-5502X/4X AN549 IB10

    TAFCSB500F48

    Abstract: EHT generation circuit diagram k3210 AN5491K Divide-by-15 horizontal output circuit with EHT Capacitor 0.01 uF
    Text: ICs for TV AN5491K Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television • Supports the multiple-point horizontal frequency 15.7 kHz to 62.7 kHz • Horizontal duty is controllable by external voltage.


    Original     		PDF AN5491K AN5491K TAFCSB500F48 TAFCSB500F48 EHT generation circuit diagram k3210 Divide-by-15 horizontal output circuit with EHT Capacitor 0.01 uF

    explain phase failure relay

    Abstract: IB10 AN549
    Text: The HC-5502X/4X Telephone Subscriber Line Interface Circuits SLIC Application Note January 1997 AN549.1 Author: Geoff Phillips Introduction The HC-5502X/4X family of telephone subscriber line interface circuits (SLIC) integrate most of the BORSCHT functions of the traditional hybrid transformer interface circuits


    Original     		PDF HC-5502X/4X AN549 explain phase failure relay IB10

    bzx 850

    Abstract: bzx 850 30
    Text: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses


    Original     		PDF CY7C1412AV18 CY7C1414AV18 CY7C1412AV18, CY7C1414AV18 bzx 850 bzx 850 30

    CY7C2663KV18

    Abstract: CY7C2665KV18 3M Touch Systems CY7C2663KV18-450BZXC
    Text: CY7C2663KV18, CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		PDF CY7C2663KV18, CY7C2665KV18 144-Mbit 550-MHz CY7C2663KV18: CY7C2665KV18: CY7C2663KV18 CY7C2665KV18 3M Touch Systems CY7C2663KV18-450BZXC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:


    Original     		PDF CY7C1568KV18/CY7C1570KV18 72-Mbit CY7C1568KV18 CY7C1570KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports


    Original     		PDF CY7C2642KV18/CY7C2644KV18 144-Mbit 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1643KV18/CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features • Offered in both Pb-free and non Pb-free packages Separate independent read and write data ports


    Original     		PDF CY7C1643KV18/CY7C1645KV18 144-Mbit 450-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original     		PDF CY7C1319KV18/CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz CY7C1321KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports


    Original     		PDF CY7C1163KV18/CY7C1165KV18 18-Mbit 550-MHz CY7C1165KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth


    Original     		PDF CY7C1423KV18/CY7C1424KV18 36-Mbit CY7C1423KV18 CY7C1424KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.0 cycles:


    Original     		PDF CY7C1548KV18/CY7C1550KV18 72-Mbit 450-MHz CY7C1548KV18 CY7C1550KV18

    CY7C1620KV18-250BZXC

    Abstract: No abstract text available
    Text: CY7C1618KV18, CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18, 8 M × 36 CY7C1618KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth


    Original     		PDF CY7C1618KV18, CY7C1620KV18 144-Mbit CY7C1618KV18 CY7C1620KV18-250BZXC

    Untitled

    Abstract: No abstract text available
    Text: CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36)


    Original     		PDF CY7C2168KV18/CY7C2170KV18 18-Mbit 550-MHz CY7C2168KV18 CY7C2170KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1243KV18/CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C1243KV18/CY7C1245KV18 36-Mbit CY7C1245KV18

    CY7C1570KV18

    Abstract: No abstract text available
    Text: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:


    Original     		PDF CY7C1568KV18/CY7C1570KV18 72-Mbit CY7C1568KV18 CY7C1570KV18 CY7C1570KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)


    Original     		PDF CY7C1347G CY7C1347G

    Untitled

    Abstract: No abstract text available
    Text: CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36)


    Original     		PDF CY7C2268KV18/CY7C2270KV18 36-Mbit CY7C2268KV18 CY7C2270KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:


    Original     		PDF CY7C1148KV18/CY7C1150KV18 18-Mbit 450-MHz CY7C1148KV18 CY7C1150KV18

    12v relay 8 pin diagram

    Abstract: No abstract text available
    Text: H April 1999 C - 5 5 File Num ber 2 B 1 4127.2 SLIC Subscriber Line Interface Circuit Features The Harris SLIC incorporates many of the BORSHT function on a single 1C chip. This includes DC battery feed, a ring relay driver, supervisory and hybrid functions. This device is


    OCR Scan     		PDF HC-5502B 1-800-4-HARRIS 12v relay 8 pin diagram