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    Alliance Memory Inc AS7C33128NTD32B-166TQC

    4Mb SYNC SRAM 128K x 32 3.3V No Turn Around Delay 100Pin TQFP 166MHz Commercial Temp
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    Karl Kruse GmbH & Co KG AS7C33128NTD32B-166TQC 2,370
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    AS7C33128NTD32B Datasheets (14)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    AS7C33128NTD32B Alliance Semiconductor 3.3V 256K x 18 pipeline burst synchronous SRAM Original PDF
    AS7C33128NTD32B Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-133TQC Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-133TQCN Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-133TQI Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-133TQIN Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-166TQC Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-166TQCN Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-166TQI Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-166TQIN Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-200TQC Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-200TQCN Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-200TQI Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF
    AS7C33128NTD32B-200TQIN Alliance Semiconductor 3.3V 128K x 32/36 Pipelined SRAM with NTD Original PDF

    AS7C33128NTD32B Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    X3231

    Abstract: No abstract text available
    Text: December 2004 AS7C33128NTD32B AS7C33128NTD36B 3.3V 128Kx32/36 Pipelined SRAM with NTDTM Features • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ


    Original     		PDF AS7C33128NTD32B AS7C33128NTD36B 100-pin X3231

    Untitled

    Abstract: No abstract text available
    Text: February 2004 AS7C33128NTD32B AS7C33128NTD36B 3.3V 128Kx32/36 SRAM with NTDTM Features • Organization: 131,072 words × 32 or 36 bits NTD 1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0 ns


    Original     		PDF AS7C33128NTD32B AS7C33128NTD36B 100-pin

    Untitled

    Abstract: No abstract text available
    Text: December 2003 AS7C33128NTD32B AS7C33128NTD36B 3.3V 128Kx32/36 SRAM with NTDTM Features • Organization: 131,072 words × 32 or 36 bits NTD 1 architecture for efficient bus operation • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns


    Original     		PDF AS7C33128NTD32B AS7C33128NTD36B 100-pin

    AS7C33128NTD32B

    Abstract: AS7C33128NTD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B
    Text: February 2005 AS7C33128NTD32B AS7C33128NTD36B 3.3V 128Kx32/36 Pipelined SRAM with NTDTM Features • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ


    Original     		PDF AS7C33128NTD32B AS7C33128NTD36B 100-pin AS7C33128NTD32B AS7C33128NTD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B

    Untitled

    Abstract: No abstract text available
    Text: February 2005 AS7C33128NTF32B AS7C33128NTF36B 3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 131,072 words × 32 or 36 bits NTD architecture for efficient bus operation


    Original     		PDF AS7C33128NTF32B AS7C33128NTF36B 100-pin

    Untitled

    Abstract: No abstract text available
    Text: December 2004 AS7C33256NTD18B 3.3V 256Kx18 Pipelined SRAM with NTDTM Features • Organization: 262,144 words × 18 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns


    Original     		PDF AS7C33256NTD18B 100-pin

    AS7C33128PFD32B

    Abstract: AS7C33128PFS32B AS7C33128PFS36B AS7C33256NTF18B AS7C33256PFD18B AS7C33256PFS18B AS7C33256
    Text: April 2005 AS7C33256NTF18B 3.3V 256K x 18 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 262,144 words x 18 bits NTD architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns


    Original     		PDF AS7C33256NTF18B 100-pin AS7C33128PFD32B AS7C33128PFS32B AS7C33128PFS36B AS7C33256NTF18B AS7C33256PFD18B AS7C33256PFS18B AS7C33256

    AS7C33128PFD32B

    Abstract: AS7C33128PFS32B AS7C33128PFS36B AS7C33256FT18B AS7C33256PFD18B AS7C33256PFS18B AS7C33256
    Text: AS7C33256FT18B December 2004 3.3V 256K x 18 Flow Through Synchronous SRAM Features • • • • • • • • • • • • • Organization: 262,144 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns


    Original     		PDF AS7C33256FT18B 100-pin AS7C33128PFD32B AS7C33128PFS32B AS7C33128PFS36B AS7C33256FT18B AS7C33256PFD18B AS7C33256PFS18B AS7C33256

    1H08S

    Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
    Text: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -


    Original     		PDF ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA IMP1232LPEMA ASM1232LPN 1H08S PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR

    ADM809RAR

    Abstract: AS7C256A hsbga 416 lcd cross reference IDT CYPRESS CROSS REFERENCE clocks DS1232* watch dog timer Product Selector Guide mbg* sot143 FS781 IDT74SSTV16857
    Text: DISCLAIMER Alliance Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Alliance Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied


    Original     		PDF IS61LV25616AL IS61LV5128AL IS61LV6416 IS61C6416 IS61LV1024 48-pin AS9C25256M2036L AS9C25512M2018L 512Kx18 ADM809RAR AS7C256A hsbga 416 lcd cross reference IDT CYPRESS CROSS REFERENCE clocks DS1232* watch dog timer Product Selector Guide mbg* sot143 FS781 IDT74SSTV16857

    AS7C33128

    Abstract: No abstract text available
    Text: AS7C33128FT32B AS7C33128FT36B December 2004 3.3V 128K x 32/36 Flow Through Synchronous SRAM Features • • • • • • • • • • • • • Organization: 131,072 words × 32 or 36 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns


    Original     		PDF AS7C33128FT32B AS7C33128FT36B 100-pin AS7C33128

    AS7C33128PFS36B-200TQI

    Abstract: AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B
    Text: December 2004 AS7C33128PFS32B AS7C33128PFS36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 131,072 words x 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns


    Original     		PDF AS7C33128PFS32B AS7C33128PFS36B 100-pin AS7C33128PFS36B-200TQI AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B

    AS7C33128NTF32B

    Abstract: AS7C33128NTF36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B
    Text: April 2005 AS7C33128NTF32B AS7C33128NTF36B 3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 131,072 words × 32 or 36 bits NTD architecture for efficient bus operation


    Original     		PDF AS7C33128NTF32B AS7C33128NTF36B 100-pin 17ilable AS7C33128NTF32B AS7C33128NTF36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B

    AS7C33128PFD32B

    Abstract: AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B
    Text: AS7C33256PFS18B December 2004 3.3V 256K x 18 pipeline burst synchronous SRAM Features • • • • • • • • • • • • • • • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns


    Original     		PDF AS7C33256PFS18B 100-pin AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B

    Untitled

    Abstract: No abstract text available
    Text: February 2005 AS7C33256NTF18B 3.3V 256K x 18 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 262,144 words x 18 bits NTD architecture for efficient bus operation Fast clock to data access: 6.5/7.5/8.0/10.0 ns


    Original     		PDF AS7C33256NTF18B 100-pin AS7C33256NTF18B

    AS7C33128

    Abstract: No abstract text available
    Text: October 2003 AS7C33128PFS32B AS7C33128PFS36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 131,072 words x 32 or 36 bits Fast clock speeds to 200 MHz in LVTTL/LVCMOS Fast clock to data access: 3.0/3.5/4.0 ns


    Original     		PDF AS7C33128PFS32B AS7C33128PFS36B AS7C33128PFD32B/ AS7C33128PFD36B) 100-pin AS7C33128

    AS7C33128FT36B

    Abstract: AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B
    Text: AS7C33128FT32B AS7C33128FT36B February 2005 3.3V 128K x 32/36 Flow Through Synchronous SRAM Features • • • • • • • • • • • • • Organization: 131,072 words × 32 or 36 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns


    Original     		PDF AS7C33128FT32B AS7C33128FT36B 100-pin AS7C33128FT36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B

    Untitled

    Abstract: No abstract text available
    Text: February 2004 AS7C33128PFS32B AS7C33128PFS36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 131,072 words x 32 or 36 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/4.0 ns


    Original     		PDF AS7C33128PFS32B AS7C33128PFS36B AS7C33128PFD32B/ AS7C33128PFD36B) 100-pin

    Untitled

    Abstract: No abstract text available
    Text: December 2004 AS7C33128NTF32B AS7C33128NTF36B 3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 131,072 words × 32 or 36 bits NTD architecture for efficient bus operation


    Original     		PDF AS7C33128NTF32B AS7C33128NTF36B 100-pin

    AS7C33128PFD32B

    Abstract: AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B
    Text: February 2005 AS7C33128PFD32B AS7C33128PFD36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 131,072 words x 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns


    Original     		PDF AS7C33128PFD32B AS7C33128PFD36B 100-pin AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B

    AS7C33128PFD32B

    Abstract: AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B
    Text: AS7C33256PFD18B February 2005 3.3V 256K x 18 pipeline burst synchronous SRAM Features • • • • • • • • • • • • • • • Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns


    Original     		PDF AS7C33256PFD18B 100-pin AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33256PFS18B

    AS7C33128NTD32B

    Abstract: AS7C33128NTD36B AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B CE01
    Text: April 2004 AS7C33128PFD32B AS7C33128PFD36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • • • • • • • • • • • • • • Organization: 131,072 words x 32 or 36 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/4.0 ns


    Original     		PDF AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B/ AS7C33128PFS36B) 100-pin AS7C33128NTD32B AS7C33128NTD36B AS7C33128PFD32B AS7C33128PFD36B AS7C33128PFS32B AS7C33128PFS36B CE01

    AS7C33128PFS36B

    Abstract: AS7C33256NTD18B AS7C33256PFD18B AS7C33256PFS18B AS7C33128PFD32B AS7C33128PFS32B
    Text: February 2005 AS7C33256NTD18B 3.3V 256Kx18 Pipelined SRAM with NTDTM Features • Organization: 262,144 words × 18 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns


    Original     		PDF AS7C33256NTD18B 100-pin AS7C33128PFS36B AS7C33256NTD18B AS7C33256PFD18B AS7C33256PFS18B AS7C33128PFD32B AS7C33128PFS32B