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    Texas Instruments CDC319DBRG4

    IC CLK BUFFER 1:10 100MHZ 28SSOP
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    DigiKey CDC319DBRG4 Reel 2,000
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    Win Source Electronics CDC319DBRG4 3,120
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    CDC319DBRG4 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CDC319DBRG4 Texas Instruments 1-Line to 10-Line Clock Driver with I2C Control Interface Original PDF
    CDC319DBRG4 Texas Instruments 1-Line to 10-Line Clock Driver with I2C Control Interface 28-SSOP 0 to 70 Original PDF

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    CDC319

    Abstract: CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150
    Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


    Original
    PDF CDC319 10-LINE SCAS590A 1-to-10 MIL-STD-883, 28-Pin CDC319 CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150

    CDC319

    Abstract: CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150
    Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


    Original
    PDF CDC319 10-LINE SCAS590A 1-to-10 MIL-STD-883, 28-Pin CDC319 CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150

    CDC319

    Abstract: CDC319DB CDC319DBR CDC319DBRG4 MO-150
    Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


    Original
    PDF CDC319 10-LINE SCAS590A 1-to-10 MIL-STD-883, 28-Pin CDC319 CDC319DB CDC319DBR CDC319DBRG4 MO-150

    Untitled

    Abstract: No abstract text available
    Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


    Original
    PDF CDC319 10-LINE SCAS590A 1-to-10 MIL-STD-883, 28-Pin