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CY7C11701KV18 Price and Stock

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Rochester Electronics LLC CY7C11701KV18-400BZXC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C11701KV18-400BZXC	Tray	541		8	1 - 10 $39.33 100 $39.33 1000 $39.33 10000 $39.33	Buy Now
Rochester Electronics LLC CY7C11701KV18-450BZXC DDR SRAM, 512KX36, 0.45NS, CMOS,
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C11701KV18-450BZXC	Bulk	265		8	1 - 10 $39.33 100 $39.33 1000 $39.33 10000 $39.33	Buy Now
Infineon Technologies AG CY7C11701KV18-400BZXC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C11701KV18-400BZXC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Cypress Semiconductor CY7C11701KV18-400BZXC DDR SRAM, 512KX36, 0.45ns PBGA165 '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	CY7C11701KV18-400BZXC		541		1	1 $39.71 10 $39.71 100 $37.33 1000 $33.76 10000 $33.76	Buy Now
Cypress Semiconductor CY7C11701KV18-450BZXC DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165 '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	CY7C11701KV18-450BZXC		265		1	1 $39.71 10 $39.71 100 $37.33 1000 $33.76 10000 $33.76	Buy Now

CY7C11701KV18 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C11701KV18-400BZXC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 400MHZ 165FBGA		Original	PDF

CY7C11701KV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
3M Touch Systems Abstract: No abstract text available Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • 18-Mbit density (2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36)	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11771KV18, CY7C11701KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11771KV18, CY7C11701KV18 CY7C11661KV18)
3M Touch Systems Abstract: No abstract text available Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • 18-Mbit density (2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36)	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11771KV18, CY7C11701KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11771KV18, CY7C11701KV18 CY7C11661KV18)
CY7C11681KV18 Abstract: 3M Touch Systems Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11681KV18 3M Touch Systems
3M Touch Systems Abstract: No abstract text available Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11771KV18, CY7C11701KV18 CY7C11661KV18) 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11771KV18, CY7C11701KV18 CY7C11661KV18)
3M Touch Systems Abstract: No abstract text available Text: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • 18-Mbit density (2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36)	Original	PDF	CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit CY7C11771KV18, CY7C11701KV18 3M Touch Systems