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    CY7C133 Price and Stock

    Rochester Electronics LLC CY7C1339A-100ACT

    IC SRAM 4MBIT PAR 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1339A-100ACT Bulk 6,750 87
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    Rochester Electronics LLC CY7C1338B-100BGCT

    IC SRAM 4MBIT PAR 119PBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1338B-100BGCT Bulk 3,000 59
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    Rochester Electronics LLC CY7C1333-50AC

    IC SRAM 2MBIT PAR 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1333-50AC Bulk 2,689 47
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    Rochester Electronics LLC CY7C1334-80AC

    IC SRAM 2MBIT PARALLEL 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1334-80AC Bulk 2,525 67
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    Rochester Electronics LLC CY7C1334-50ACT

    IC SRAM 2MBIT PAR 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1334-50ACT Bulk 1,500 70
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    Find more CY7C133 price and stock on Findchips.com

    CY7C133 Datasheets (298)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C133 Cypress Semiconductor 2K x 16 Dual-Port Static RAM Original PDF
    CY7C133 Cypress Semiconductor 2K x 16 Dual-Port Static RAM Original PDF
    CY7C133 Unknown 2K x 16 Dual-Port Static RAM Original PDF
    CY7C1330 Cypress Semiconductor 64K x 32 Synchronous-Pipelined Cache RAM Original PDF
    CY7C1330-100AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1330-100AC Cypress Semiconductor 64K x 32 Synchronous-Pipelined Cache RAM Scan PDF
    CY7C1330-117AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1330-117AC Cypress Semiconductor 64K x 32 Synchronous-Pipelined Cache RAM Scan PDF
    CY7C1330-66AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1330-66AC Cypress Semiconductor 64K x 32 Synchronous-Pipelined Cache RAM Scan PDF
    CY7C1330AV25 Cypress Semiconductor 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write Original PDF
    CY7C1330AV25-250BGC Cypress Semiconductor 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write Original PDF
    CY7C1330L-100AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1330L-100AC Cypress Semiconductor 64K x 32 Synchronous-Pipelined Cache RAM Scan PDF
    CY7C1330L-117AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1330L-117AC Cypress Semiconductor 64K x 32 Synchronous-Pipelined Cache RAM Scan PDF
    CY7C1330L-66AC Cypress Semiconductor Cache Memory Original PDF
    CY7C1330L-66AC Cypress Semiconductor 64K x 32 Synchronous-Pipelined Cache RAM Scan PDF
    CY7C1331 Cypress Semiconductor 64K x 18 Synchronous Cache 3.3V RAM Original PDF
    CY7C1331-10JC Cypress Semiconductor Cache Memory Original PDF
    ...

    CY7C133 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1339

    Abstract: No abstract text available
    Text: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary


    Original     		PDF CY7C1339 CY7C1339 100-MHz 166-MHz

    64KX32

    Abstract: 7C1334-100 7C1334-133 7C1334-50 7C1334-80 CY7C1334
    Text: fax id: 1084 CY7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture Features • Low 16.5 mW standby power Functional Description • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P • Supports 133-MHz bus operations with zero wait states


    Original     		PDF CY7C1334 64Kx32 MT55L64L32P 133-MHz CY7C1334 7C1334-100 7C1334-133 7C1334-50 7C1334-80

    80486 microprocessor block diagram and pin diagram

    Abstract: 64KX32 CY7C1336
    Text: 36 PRELIMINARY CY7C1336 64K x 32 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 66-MHz microprocessor cache systems with zero wait states • 64K by 32 common I/O • Low Standby Power 1.65 mW, L version • Fast clock-to-output times


    Original     		PDF CY7C1336 66-MHz 117-MHz 100-pin CY7C1336 80486 microprocessor block diagram and pin diagram 64KX32

    7C13

    Abstract: CY7C1335
    Text: fax id: 1045 1CY 7C13 35 PRELIMINARY CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 660 µW standby power (f=0, L version) The CY7C1335 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary


    Original     		PDF CY7C1335 CY7C1335 100-MHz 7C13

    80486 microprocessor block diagram and pin diagram

    Abstract: CY7C1338B
    Text: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence


    Original     		PDF CY7C1338B 117-MHz 100-pin CY7C1338B 80486 microprocessor block diagram and pin diagram

    C133-10

    Abstract: C1336 C133-14 CY7C133 CY7C143 IDT7133 IDT7143
    Text: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns


    Original     		PDF CY7C133 CY7C143 65-micron CY7C133 CY7C133; 68-pin IDT7133 IDT7143 C133-10 C1336 C133-14 CY7C143 IDT7133 IDT7143

    CY7C1338B

    Abstract: 80486 microprocessor block diagram and pin diagrams
    Text: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence


    Original     		PDF CY7C1338B 117-MHz 100-pin CY7C1338B BG119) 80486 microprocessor block diagram and pin diagrams

    64KX32

    Abstract: CY7C1336
    Text: 336 PRELIMINARY CY7C1336 64K x 32 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 66-MHz microprocessor cache systems with zero wait states • 64K by 32 common I/O • Low Standby Power 1.65 mW, L version • Fast clock-to-output times


    Original     		PDF CY7C1336 66-MHz 117-MHz 100-pin CY7C1336 64KX32

    wa8k

    Abstract: CY7C1330AV25 CY7C1330AV25-250BGC CY7C1332AV25
    Text: CY7C1330AV25 CY7C1332AV25 PRELIMINARY 18-Mbit 512K x 36/1Mbit x 18 Pipelined Register-Register Late Write Features Functional Description • Fast clock speed: 250, 200 MHz • Fast access time: 2.0, 2.25 ns • Synchronous Pipelined Operation with Self-timed Late


    Original     		PDF CY7C1330AV25 CY7C1332AV25 18-Mbit 36/1Mbit CY7C1330AV25 CY7C1332AV25 CY7C1330AV25/CY7C1332AV25 wa8k CY7C1330AV25-250BGC

    CY7C1338G

    Abstract: No abstract text available
    Text: CY7C1338G 4-Mbit 128K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 128K x 32 common I/O • 3.3V core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate


    Original     		PDF CY7C1338G 133-MHz 100-Pin 119-Ball CY7C1338G

    CY7C1339G

    Abstract: No abstract text available
    Text: CY7C1339G 4-Mbit 128K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are


    Original     		PDF CY7C1339G CY7C1339G

    Untitled

    Abstract: No abstract text available
    Text: CY7C1339G PRELIMINARY 4-Mbit 128K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 32 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times


    Original     		PDF CY7C1339G 250-MHz 200-MHz 166-MHz 133-MHz 100-pin 119-ball CY7C133istory CY7C1339G

    Untitled

    Abstract: No abstract text available
    Text: CY7C1339G PRELIMINARY 4-Mbit 128K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 32 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times


    Original     		PDF CY7C1339G 250-MHz 200-MHz 166-MHz 133-MHz 100-pin 119-ball CY7C133

    20306

    Abstract: No abstract text available
    Text: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous


    Original     		PDF CY7C1333F 117-MHz 100-MHz CY7C1333F 20306

    Untitled

    Abstract: No abstract text available
    Text: CY7C1336H PRELIMINARY 2-Mbit 64K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 32 common I/O • 3.3V core power supply • 3.3V I/O supply • Fast clock-to-output times — 6.5 ns (133-MHz version) — 8.0 ns (100-MHz version)


    Original     		PDF CY7C1336H 133-MHz 100-MHz 100-pin CY7C1336H

    CY7C1339F

    Abstract: CY7C1339F-225AC CY7C1339F-225BGC CY7C1339F-250AC CY7C1339F-250AI CY7C1339F-250BGC CY7C1339F-250BGI
    Text: CY7C1339F 4-Mbit 128K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 32 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times


    Original     		PDF CY7C1339F 250-MHz 225-MHz 200-MHz CY7C1339F -133AI CY7C1339F-225AC CY7C1339F-225BGC CY7C1339F-250AC CY7C1339F-250AI CY7C1339F-250BGC CY7C1339F-250BGI

    m3351

    Abstract: KD 2114 marking code J2UT 1203 6d t201 CY7C1339 EQUIVALENT cd 1031 cs
    Text: CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V DDq=2.5V. * Supports 100-MHz bus fo r Pentium and PowerPC operations w ith zero w ait states


    OCR Scan     		PDF CY7C1339 100-MHz 166-MHz 133-MHz CY7C1339 m3351 KD 2114 marking code J2UT 1203 6d t201 EQUIVALENT cd 1031 cs

    CY7C1333

    Abstract: No abstract text available
    Text: CYPRESS _ CY7C1333 6~Kx3? Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin c o m p a tib le and fu n c tio n a lly eq u iv alen t to ZB T™ d evic e M T 55L 64 L 32F • S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w a it sta tes


    OCR Scan     		PDF MT55L64L32F 66-MHz 50-MHz 100-pin CY7C1333

    Untitled

    Abstract: No abstract text available
    Text: fax id: 1084 W CYPRESS CY7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture Features Functional Description • S u p p o rts 13 3 -M H z b u s o p e ratio n s w ith zero w ait sta tes— D ata is tra n s ferred on ev e ry clo ck T he C Y 7 C 1 334 is a 3.3V 64K by 32 syn ch ron ous-p ip eline d


    OCR Scan     		PDF CY7C1334 64Kx32

    MAV5

    Abstract: No abstract text available
    Text: fax id: 1084 ^ CY7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture • Low 16.5 mW standby power Features • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P • Supports 133-MHz bus operations with zero wait states


    OCR Scan     		PDF CY7C1334 64Kx32 MT55L64L32P 133-MHz CY7C1334 MAV5

    Untitled

    Abstract: No abstract text available
    Text: fax id: 1088 CY7C1333 ADVANCED INFORMATION 64Kx32 Flow-Through SRAM with NoBL Architecture Features Functional Description • S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w ait sta tes— D ata is tra n s ferred on ev e ry clock • In te rn ally se lf-tim e d o u tp u t b u ffe r co n tro l to elim in a te


    OCR Scan     		PDF CY7C1333 64Kx32

    Untitled

    Abstract: No abstract text available
    Text: fax id : 1084 CY7C1334 64Kx32 Pipelined SRAM with NoBL Architecture Featu res Functional Description • Supports 133-MHz bus operations with zero wait states— Data is transferred on every clock • Internally self-timed output buffer control to eliminate


    OCR Scan     		PDF CY7C1334 64Kx32 133-MHz 100-MHz 80-MHz r50-M

    2930D

    Abstract: No abstract text available
    Text: fax id: 1108 CY7C1338 :/ C Y P R E S S 128K X 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • S u p p o rts 117-MHz m ic ro p ro c e s s o r cache s y s te m s w ith zero w a it states • 128K by 32 co m m o n I/O • Low S ta n d b y Pow er 1.65 mW, L v e rs io n


    OCR Scan     		PDF 117-MHz 2930D

    00Q01

    Abstract: ZQ50A BWRO
    Text: PRELIMINARY CY7C1337 32K x 32 Synchronous-Pipelined Cache RAM Features • Low 660 |xW standby power (f=0, L version) • Supports 117-MHz bus operations with zero wait states • Fully registered Inputs and outputs for pipelined oper­ ation • 32K x 32 common I/O architecture


    OCR Scan     		PDF CY7C1337 117-MHz 100-MHz 100TQFP 00Q01 ZQ50A BWRO