ecn 1310
Abstract: No abstract text available
Text: CY7C1561KV18, CY7C1576KV18 CY7C1563KV18, CY7C1565KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:
|
Original
|
PDF
|
CY7C1561KV18,
CY7C1576KV18
CY7C1563KV18,
CY7C1565KV18
72-Mbit
CY7C1563KV18
ecn 1310
|
ecn 1310
Abstract: CY7C1565KV18-400BZI 3M Touch Systems
Text: CY7C1561KV18, CY7C1576KV18 CY7C1563KV18, CY7C1565KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:
|
Original
|
PDF
|
CY7C1561KV18,
CY7C1576KV18
CY7C1563KV18,
CY7C1565KV18
72-Mbit
CY7C1563KV18
ecn 1310
CY7C1565KV18-400BZI
3M Touch Systems
|
ecn 1310
Abstract: No abstract text available
Text: CY7C1561KV18, CY7C1576KV18 CY7C1563KV18, CY7C1565KV18 PRELIMINARY 72-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:
|
Original
|
PDF
|
CY7C1561KV18,
CY7C1576KV18
CY7C1563KV18,
CY7C1565KV18
72-Mbit
CY7C1563KV18
ecn 1310
|
3M Touch Systems
Abstract: No abstract text available
Text: CY7C1561KV18 CY7C1576KV18 CY7C1565KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports
|
Original
|
PDF
|
CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
72-Mbit
550-MHz
CY7C1576KV18:
CY7C1565KV18:
3M Touch Systems
|
3M Touch Systems
Abstract: No abstract text available
Text: CY7C1561KV18 CY7C1576KV18 CY7C1565KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports
|
Original
|
PDF
|
CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
72-Mbit
CY7C1561KV18:
CY7C1576KV18:
CY7C1565KV18:
550-MHz
3M Touch Systems
|
CY7C15632KV18
Abstract: No abstract text available
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
|
CY7C15632KV18
Abstract: CY7C15632KV18-550BZC CY7C15632KV18-400BZXI
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles: ■ 550 MHz Clock for High Bandwidth
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
CY7C15632KV18-550BZC
CY7C15632KV18-400BZXI
|
CY7C15632KV18
Abstract: No abstract text available
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • With Read Cycle Latency of 2.5 cycles: Separate Independent Read and Write Data Ports
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
|
CY7C15632KV18
Abstract: 3M Touch Systems
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
3M Touch Systems
|
CY7C1565KV18-500BZXI
Abstract: 3M Touch Systems
Text: CY7C1565KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C1565KV18
72-Mbit
72-QDR®
CY7C1565KV18:
550-MHz
CY7C1565KV18-500BZXI
3M Touch Systems
|
CY7C15632KV18
Abstract: 3M Touch Systems
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles: ■ 550 MHz Clock for High Bandwidth
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
3M Touch Systems
|
CY7C15632KV18
Abstract: 3M Touch Systems
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
3M Touch Systems
|
CY7C15632KV18
Abstract: No abstract text available
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
|
CY7C15632KV18
Abstract: No abstract text available
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Configurations Features • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
|
|
|
CY7C15632KV18
Abstract: 3M Touch Systems
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
3M Touch Systems
|
CY7C15632KV18
Abstract: No abstract text available
Text: CY7C15632KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features n Configurations Separate Independent Read and Write Data Ports p Supports concurrent transactions
|
Original
|
PDF
|
CY7C15632KV18
72-Mbit
CY7C15632KV18
|