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    ECL logic diagram

    Abstract: F10123 F10523 fairchild ECL pin diagram of 2030 TA 2030
    Text: F10123 F10523 TRIPLE BUS DRIVER F10K VOLT AGE COMPENSATED ECL DESCRIPTION — The F10123and F10523 contain three NOR gates designed fo r bus driving applications. The o utputs are designed and specified fo r driving 25 Q loads to -2.1 V. This allow s an o utput to drive a 50 Q bus term inated at both ends. Higher


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    PDF F10123 F10523 F10123and F10523 ECL logic diagram F10123 fairchild ECL pin diagram of 2030 TA 2030