PU0313
Abstract: D0301 pin DIAGRAM OF IC 7474 108 to 174 mhz C0301 LD11 LD12 LD17 LD18 la3 d20
Contextual Info: 1 2 3 4 5 6 7 8 VCC 1 R0301 100 2 1 VCCPLL VCC A C0301 22uF A 2 7 U0302 NC VCC GND OUT 14 8 VCC CLKIN OSCILLATOR 33.33 MHZ 87 85 91 182 184 40 181 PU0301 RESET~ READY960~ BTERM~ BOFF960~ HOLD960 INTUART~ INT596~ INT9060~ 93 94 95 100 101 102 106 107 108 PU0302
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R0301
C0301
U0302
PU0301
READY960~
BOFF960~
HOLD960
INT596~
INT9060~
PU0302
PU0313
D0301
pin DIAGRAM OF IC 7474
108 to 174 mhz
C0301
LD11
LD12
LD17
LD18
la3 d20
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MSL260G
Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)
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PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
MSL260G
MSL-260-G
D0806
R0807
T0803
D0802
D0807
RDD0804
D0808
5 pin reset ic ARB
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PD0404
Abstract: U0401 U0403 pu0403 DIP10 16V8R LA29 LA30 I11I12
Contextual Info: 1 2 3 4 5 6 7 8 PCLK1B LA[2.31] A LA[2.31] LA3 LA28 LA29 LA30 LA31 RESET~ ADS~ BLAST~ WAIT~ READYO~ IORDY~ RESET~ ADS~ BLAST~ WAIT~ READYO~ PU0401 PD0401 1 2 3 4 5 6 7 8 9 10 11 14 23 13 U0401 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4
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PU0401
PD0401
U0401
CS9060~
20V8R
PU0402
PU0403
PU0404
PD0402
PD0404
U0401
U0403
pu0403
DIP10
16V8R
LA29
LA30
I11I12
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D0807
Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
Contextual Info: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors
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PCI9060
PCI9060,
80960CA
82596CA
U0101
20V8R
U0102
PCI9060
D0807
C0702
D0801
D0806
R0807
T0803
D0808
D0802
RDD0804
C0705
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u1001
Abstract: transistor R1001 16v8c J1001 R1001 PU1003 34x2 U0303F PU1002 c1001
Contextual Info: 1 2 3 4 5 6 7 8 LD[0.31] LBE~[0.3] LA[2.31] LD[0.31] LBE~[0.3] LA[2.31] J1002 J1001 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 LBE~0 LBE~1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14
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J1002
J1001
READY960~
INT596~
U0303F
74ACT14
PU1002
C1001
C1002
TL7705A
u1001
transistor R1001
16v8c
J1001
R1001
PU1003
34x2
U0303F
PU1002
c1001
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16v8 book
Abstract: BREQ9060 BREQ960 596CA
Contextual Info: "* "*Proprietary Rights Notice: * "* * "*This material contains the valuable proprietary and trade * "*secret information of PLX of Mountain View, California. * "*No part of such information *
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1N4148/2 pin connector sip
Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
Contextual Info: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000
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PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
1N4148/2 pin connector sip
ACT04 MOTOROLA
1N4148 D0805
pal programming
sw dip-3
80960CA
15 pin through hole d sub connector
16v8h
DIODE MOTOROLA B33
D0805
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D0802
Abstract: D0807 C0702 16v8c T0803 D0806 R0807 D0808 RDD0804 pt3868
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 20V8R DIP 9 U0102 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11
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U0101
20V8R
U0102
PCI9060,
80960CA
82596CA
PCI9060
PCI9060
D0802
D0807
C0702
16v8c
T0803
D0806
R0807
D0808
RDD0804
pt3868
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7705 reset
Abstract: BREQ9060 BREQ960 h20000008
Contextual Info: "* "*Proprietary Rights Notice: * "* * "*This material contains the valuable proprietary and trade * "*secret information of PLX of Mountain View, California. * "*No part of such information *
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