AN1091
Abstract: MPC932 MPC932P
Text: MOTOROLA Order this document by MPC932P/D SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver MPC932P The MPC932P is a 3.3V compatible PLL based clock driver device targetted for zero delay applications. The device provides 6 outputs for driving clock loads plus a single dedicated PLL feedback clock output.
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MPC932P/D
MPC932P
MPC932P
BR1333
AN1091
MPC932
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PDF
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AN1091
Abstract: MPC932 MPC932P
Text: MOTOROLA Order this document by MPC932P/D SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver MPC932P The MPC932P is a 3.3V compatible PLL based clock driver device targetted for zero delay applications. The device provides 6 outputs for driving clock loads plus a single dedicated PLL feedback clock output.
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Original
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MPC932P/D
MPC932P
MPC932P
BR1333
AN1091
MPC932
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PDF
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Z9104
Abstract: IMIZ9104DAB IMIZ9104DABT MPC932P SC25
Text: Z9104 Variable Delay Motherboard Clock Buffer Features Table 1. Feedback Scale Select Codes Mode • Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path • Two-kV ESD protected • Six low-skew clocks generated
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Original
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Z9104
32-lead
MPC932P
Z9104
IMIZ9104DAB
IMIZ9104DABT
MPC932P
SC25
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PDF
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Untitled
Abstract: No abstract text available
Text: Z9104 Variable Delay Motherboard Clock Buffer Features Table 1. Feedback Scale Select Codes • Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path • 2 kV ESD protected • 6 low-skew clocks generated
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Original
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Z9104
32-Lead
MPC932P
Z9104
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PDF
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NEC 9902
Abstract: PLL52C32-01 50MHZ MPC932P 9902 ST
Text: PLL52C32-01 Low Volt age PLL Clock Drivers The PLL52C32-01 is a 3.3V / 2.5V compatible PLL based clock driver device targeted for Zero Delay applications. PIN INFORMATION The device provides 6 outputs for driving clock loads plus a single dedicated PLL feedback clock
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PLL52C32-01
PLL52C32-01
100ps
NEC 9902
50MHZ
MPC932P
9902 ST
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PDF
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MPC932P
Abstract: No abstract text available
Text: PLL102-01 Low Voltage PLL Clock Drivers Q5 VCCO VSSO Q4 VCCO Q3 25 24 23 22 21 20 19 18 17 16 VCCQ0 26 15 QFB Q0 27 14 VCCO_QFB VSSO 28 SD1:2 29 SD0 VSS0_QFB 13 FB_IN 12 SD3 30 11 SD4 MODE 31 10 VCCA 32 9 SD5 VSSA 1 2 3 4 5 6 7 8 FBSEL0 FBSEL1 MR/OE COM_SD
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PLL102-01
133MHz.
MPC932P.
MPC932P
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PDF
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Untitled
Abstract: No abstract text available
Text: Z9104 Variable Delay Motherboard Clock Buffer Features Table 1. Feedback Scale Select Codes Mode • Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path • Two-kV ESD protected • Six low-skew clocks generated
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Original
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Z9104
32-lead
MPC932P
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PDF
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