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TE Connectivity MPY112KJ4C Multiplier, Bipolar, CDIP48
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MPY112K Datasheets (3)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
MPY112K		TRW LSI Products	Data Converters Data Book 1990		Scan	PDF
MPY112KJ4A		TRW LSI Products	Data Converters Data Book 1990		Scan	PDF
MPY112KJ4C		TRW LSI Products	Data Converters Data Book 1990		Scan	PDF

MPY112K Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
LMU112 Abstract: LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K Text: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned	Original	LMU112 12-bit MPY112K 48-pin 52-pin LMU112 LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K	PDF
LMU112 Abstract: LMU112DC50 LMU112DC60 LMU112PC25 LMU112PC50 LMU112PC60 MPY112K Text: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ DESCRIPTION 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY112K Two’s Complement or Unsigned	Original	LMU112 12-bit MPY112K MIL-STD-883, 48-pin 52-pin LMU112 LMU112DC50 LMU112DC60 LMU112PC25 LMU112PC50 LMU112PC60 MPY112K	PDF
LMU112 Abstract: LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K R13NC 212109 Text: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned	Original	LMU112 12-bit MPY112K 48-pin 52-pin LMU112 LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K R13NC 212109	PDF
Untitled Abstract: No abstract text available Text: LMU112 12 x 12-bit Parallel Multiplier D E V I C E S IN C O R P O R A T E D \|FEATURES DESCRIPTION The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with TRW's MPY112K.	OCR Scan	LMU112 12-bit LMU112 MPY112K. MPY112K MIL-STD-883, LMU112DC60 LMU112PC60	PDF
U112D Abstract: No abstract text available Text: L M U 1 1 2 Features_ Description_ □ 50 ns worst-case multiply time The LMU112 is a high-speed, low power, 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with TRW's MPY112K.	OCR Scan	LMU112 12-bit MPY112K. MPY112K MIL-STD883, 48-pin U112D	PDF
Untitled Abstract: No abstract text available Text: L O G IC D E V IC E S EbE IN C D • S S b S IG S DG 01231 _ _ 12 x 12-bit Parallel Multiplier FEATURES 5 WÊ r - f ? - LM U 1 1 2 DESCRIPTION □ 50 ns Worst-Case Multiply Time □ Low Power CMOS Technology □ Replaces TRW MPY112K	OCR Scan	12-bit MPY112K M1L-STD883, 48-pin 52-pin LMU112 MPY112K.	PDF
LMU11250 Abstract: LMU112 MPY112K bio39 Text: LMU112 Features Description □ 50 ns worst-case m ultiply time The LMU112 is a high-speed, low pow er, 12-bit parallel m ultiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible w ith TRW 's MPY112K. □ Low-power CMOS technology	OCR Scan	LMU112 MPY112K MIL-STD-883, 48-pin LMU112 12-bit MPY112K. LMU11250 MPY112K bio39	PDF
112KJ4C Abstract: MPY112K 112kj4 trw mpy 16 MPY112 MPY012H MPY112KJ4A MPY112KJ4C TRW LSI Products 112kj Text: MPY112K r n Multiplier Features 12x12 Bit, 50ns • 50ns Multiply Time Worst Case The MPY112K is a video-speed 12x12 bit parallel multiplier which operates at a 50ns cycle time (20MHz multiplication rate). The multiplicand and the multiplier may be specified together as two's complement or	OCR Scan	MPY112K 12x12 MPY112K 20MHz 16-bit 112KJ4A 112KJ4C 112kj4 trw mpy 16 MPY112 MPY012H MPY112KJ4A MPY112KJ4C TRW LSI Products 112kj	PDF
Untitled Abstract: No abstract text available Text: LM U112 12 x 12-bit Parallel Multiplier FEATURES □ 25 ns W orst-Case Multiply Time □ Low Power CMOS Technology □ Replaces TRW MPY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Available 100% Screened to MIL-STD-883, Class B	OCR Scan	12-bit MPY112K MIL-STD-883, 48-pin 52-pin LMU112 LMU112 MPY112K.	PDF
MPY112K Abstract: No abstract text available Text: MPY112K Multiplier 1 2 x 1 2 Bit, 50ns The MPY112K is a video-speed 1 2 x 1 2 bit parallel m ultiplier w h ich operates at a 50ns cycle tim e 20M H z m ultiplication rate . The m ultiplicand and th e m ultiplier may be specified to g e th e r as tw o 's com plem ent or	OCR Scan	MPY112K MPY112K 16-bit	PDF
R238 Abstract: No abstract text available Text: ¿oogç LMU112 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D FEATURES □ □ □ □ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY112K Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Available 100% Screened to	OCR Scan	LMU112 12-bit MPY112K MIL-STD-883, 48-pin 52-pin R238	PDF
B1016 Abstract: LMU11250 Text: LMU112 12 x 12-bit Parallel Multiplier □ FV IC E S IN C O R P Q R A T F D FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Package Styles Available:	OCR Scan	LMU112 12-bit LMU112 MPY112K. LMU112JC50 LMU112JC25 LMU112PC50 LMU112PC25 B1016 LMU11250	PDF
LMU112 Abstract: 12x12-bit Text: LOGIC DEVICES INC TS M ^ S S t S l D S 0 0 0 0 ^ 1 3 T “^ " 07 LMU112 12 x 12-bit parallel multiplier general information The LMU112 is a high-speed, low power, 12-bit parallel multiplier built using advanced CMOS technology.The LMU112 is pin and functionally compatible with	OCR Scan	12-bit LMU112 sMPY112K. Incorporated628 12x12-bit	PDF
Untitled Abstract: No abstract text available Text: LMU112 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs	OCR Scan	LMU112 12-bit PY112K 48-pin 52-pin LMU112 MPY112K. LMU112JC50	PDF