SI 122 D

Abstract: AS12E
Contextual Info: M I T E L SEMICONDUCTOR 15E D I b54T37Q OOOM'iflB 2 I MITEL* MT8940 T1/CEPT Digital Trunk PLL ISO-CMOS ST-BUS FAM ILY 91 61-002-03S-N A ISSU E 3 Features Provides T1 clock a t 1.544 M Hz locked to input fram e pulse. So u rces C EP T 30 + 2 D ig ital T ru n k/S T -B U S

TVP1510

Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL* Features MT8940 T1/CEPT Digital Trunk PLL _ ISSUE 7_ July 1993 Ordering Information • • • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS

Contextual Info: M MT8940 T1 /CEPT Digital Trunk PLL ISO-CMOS ST-BUS FAMILY I T E L ISSUE 7 9161-002-035-NA July 1993 Features • Provides T1 clock at 1.544 MHz locked to input fram e pulse O rdering Inform ation MT8940AC MT8940AE • Sources CEPT 30 + 2 D igital Trunk/ST-BUS

MT8940AE1

Contextual Info: ISO-CMOS ST-BUSTM FAMILY MT8940 T1/CEPT Digital Trunk PLL Data Sheet Features September 2005 • Provides T1 clock at 1.544 MHz locked to input frame pulse • Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or external 8

Contextual Info: ISO-CMOS ST-BUS FAMILY MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 8 March 1997 Ordering Information • • • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

MH89760

Abstract: MH89760B MT8940 MT8940AC MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY  MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 7 July 1993 Ordering Information • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

MH89760

Abstract: MH89760B MT8940 MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 8 March 1997 Ordering Information • • • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

MT8980

Abstract: MT8980 application MH89760 MH89760B MT8940 MT8940AC MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY  MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 7 July 1993 Ordering Information • Provides T1 clock at 1.544 MHz locked to input frame pulse • Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

MH89760

Abstract: MH89760B MT8940 MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY  MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 8 March 1997 Ordering Information • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

CV 203

Abstract: ISS 355 MT8980 MH89760 MH89760B MT8940 MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 8 March 1997 Ordering Information • • • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

CV 203

Abstract: MH89760 MH89760B MT8940 MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY M ITEL MT8940 T1/CEPT Digital Trunk PLL Features ISSUE i M arch 1997 O rdering Inform ation Provides T1 clock at 1.544 MHz locked to input fram e pulse • Sources C EPT 30+2 D igital Trunk/ST-BUS clock and tinning signals locked to internal or

Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL* MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 7 July 1993 Ordering Information • Provides T1 clock at 1.544 MHz locked to input frame pulse • Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

Contextual Info: ISO-CMOS ST-BUS FAMILY MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 8 March 1997 Ordering Information • • • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

DPLL

Abstract: MH89760 MH89760B MT8940 MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY  MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 8 March 1997 Ordering Information • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

MH89760

Abstract: MH89760B MT8940 MT8940AE
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8940 T1/CEPT Digital Trunk PLL Features ISSUE 8 March 1997 Ordering Information • • • • • • Provides T1 clock at 1.544 MHz locked to input frame pulse Sources CEPT 30+2 Digital Trunk/ST-BUS clock and timing signals locked to internal or

Contextual Info: •I MITEL' b24^37G DDÜ7S7G SÔ2 « M I T C MT8940 T1/CEPT Digital Trunk PLL ISO-CMOS ST-BUS FAMILY Features April 1992 ISSUE 6 9161-002-035-NA Pin Connections Provides T1 clock at 1.544 M Hz locked to input fram e pulse. Sources C EP T 3 0 + 2 D ig ital T ru n k /S T -B U S

74HC12

Abstract: ST-BUS MH89760B MH89790B MT8920B MT8920BE MT8920BP MT8920BS MT8976 MT8979
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8920B ST-BUS Parallel Access Circuit  Features • • • • • • • • ISSUE 7 High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP mode 1 Fast dual-port RAM access (mode 2) Access time: 120 nsec

MT8952

Abstract: MT8976 MT8977 MT8977AC MT8977AE MT8977AP MT8979 MT8980 SLC96
Contextual Info:  ISO-CMOS ST-BUS FAMILY MT8977  T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • • • • • • • • • • • • • ISSUE 2 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance

MH89760

Abstract: MT8940 MT8941B MT8941BP1 MT8941BPR1 MT8976
Contextual Info: MT8941B Advanced T1/CEPT Digital Trunk PLL Data Sheet Features June 2008 • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse • Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock

C14B

Abstract: PMC 1601 C128H c120h EELST PE64952 68HC11 PM4341 C04FH PM6541
Contextual Info: PMC-Sierra, Inc. PM6541 E1XC-EVBD TELECOM STANDARD PRODUCT PMC-930917 ISSUE 1 E1XC EVALUATION DAUGHTERBOARD PM6541 E1XC-EVBD E1XC EVALUATION DAUGHTERBOARD ISSUE 1: DECEMBER 1997 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

MH89760

Abstract: MT8940 MT8941B MT8941BE MT8941BP MT8976
Contextual Info: CMOS ST-BUS FAMILY MT8941B Advanced T1/CEPT Digital Trunk PLL DS5186 Features ISSUE 1 June 1999 Ordering Information • • • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse Provides CEPT clock at 2.048 MHz and ST-BUS

Contextual Info: CMOS ST-BUS FAMILY MT89L85 Enhanced Digital Switch Advance Information DS5194 Features • • • • • • • • • • • 3.3 volt supply 5V tolerant inputs and TTL compatible outputs 256 x 256 channel non-blocking switch Programmable frame integrity for wideband

Contextual Info: ISO-CMOS ST-BUS FAMILY MT8979 CEPT PCM 30/CRC-4 Framer & Interface Features • • • • • • • • • • ISSUE 8 Single chip primary rate 2048 kbit/s CEPT transceiver with CRC-4 option Meets CCITT Recommendation G.704 Selectable HDB3 or AMI line code

STO1A

Abstract: MH89760B MH89790B MT8920B MT8920BE MT8920BP MT8920BS MT8976 MT8979
Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL MT8920B ST-BUS Parallel Access Circuit Features ISSUE 7 M arch 1997 • High speed parallel access to the serial ST-BUS • Parallel bus optim ized for 68000 jaP m ode 1 MT8920BE • Fast d u a l-p ort RAM access (m ode 2)