SCAS682A Search Results

CDC5801

Abstract: CDCVF2310
Text: CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS682A – OCTOBER 2002 D Low Jitter Clock Multiplier by x4, x6, x8. D D D D D D D D D D D Input Frequency Range 19 MHz to 125 MHz . Supports Output Frequency From 150 MHz to 500 MHz