CDCP1803
Abstract: CDCP1803RTHR JESD51-7 SLUA271
Text: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14
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Original
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CDCP1803
SCAS727B
800-MHz
CDCP1803
CDCP1803RTHR
JESD51-7
SLUA271
|
PDF
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CDCP1803
Abstract: CDCP1803RTHR JESD51-7 SLUA271
Text: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14
|
Original
|
CDCP1803
SCAS727B
800-MHz
CDCP1803
CDCP1803RTHR
JESD51-7
SLUA271
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14
|
Original
|
SCAS727B
CDCP1803
|
PDF
|
CDCP1803
Abstract: JESD51-7 SLUA271
Text: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14
|
Original
|
CDCP1803
SCAS727B
800-MHz
CDCP1803
JESD51-7
SLUA271
|
PDF
|