Contextual Info: SN5409, SN54LS09, SN54S09, SN7409, SN74LS09, SN74S09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS DECEMBER 1 9 8 3 -R E V IS E D M A R C H 1 9 8 8 Package Options Include Plastic "Sm all Outline" P ackages, Ceram ic Chip Carriers and Flat P ackages, and Plastic and Ceram ic

jl 54123

Abstract: SN64121
Contextual Info: TYPES SN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS R E V IS E D D E C E M B E R 1 9 8 3 SN54221, SN54LS221 . . . J OR W PACKAGE SN74221 . . J OR N PACKAGE SN74LS221 . . D, J OR N PACKAGE TOP VIEW 1A C 1 ^ J l 6

74LS169BN

Abstract: 74S169
Contextual Info: TYPES SN54LS169B, SN54S168, SN54S169, SN74LS169B, SN74S168, SN74S169 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS OCTOBER 1976 —REVISED MAY 1983 S168 . . . SYNCHRONOUS UP/DOW N DECADE COUNTERS 'LS169B, 'S169 . . . SYNCHRONOUS UP/DO W N BINARY COUNTERS SN 54S 168, 5N 54LS169B, S N 54S 169 . . . J OB W PACKAGE

7476 ic specifications

Abstract: ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
Contextual Info: SN547G, SN54LS76A, SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR D EC EM BE R 1 9 8 3 -R E V IS E D M A R C H • Dependable Texas Instruments Quality and Reliability TO P V IE W ] *^16 : i k iclkC 15 H 1 Q 1 prëC 2 14 : i q 1clrC 3 13 DGND

LVC244

Contextual Info: I SN74LVC241 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SGAS343 - MARCH 1994 DB, DW, OR PW PACKAGE TOP VIEW E P IC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C Typical V q HV (Output V qh Undershoot)

54151A

Contextual Info: TYPES SN54150, SN54151A. SN54152A, SN54LS151, SN54LS152, SN54S151, SN74150, SN741S1A, SN74LS151, SN74S151 DATA SELECTORS/MULTIPLEXERS D E C E M B E R 1 9 7 2 - R E V IS E D D E C E M B E R 1983 SN 5 41 5 0 . . J OR W PACKAG E S N 7 4 1 5 0 . . J OR N PACKAGE

Contextual Info: SN74LVC540 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS JA N U A R Y 1993 • Space-Saving Package Option: Shrink Small-Outline Package DB Features EIAJ 0.65-mm Lead Pitch DB, DW, OR PW PACKAGE (TOP VIEW) • EPIC (Enhanced-Performance implanted CMOS) Submicron Process

logic diagram of 7432

Abstract: Texas Instruments TTL 7432
Contextual Info: SN5432, SN 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 QUADRUPLE 2-INPUT POSITIVE-OR GATES DECEMBER 1983-REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs • SN 5432. SN 54LS32, SN 54S 32 . . . J OR W PACKAGE

Contextual Info: SN54LS15, SN54S15, SN74LS15, SN74S15 TRIPLE 3 INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS A P R IL 1 9 8 5 — R E V IS E D M A R C H Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

CI sn74LS05

Contextual Info: TYPES SN5405, SN54H05, SN54LS05, SN54S05, SN7405, SN74H05, SN74LS05, SN74S05 HEX INVERTERS WITH O P EN -C O LLEC TO R OUTPUTS R E V I S E D D E C E M B E R 1983 SN5405, SN54H05 . . . J PACKAGE SN54LS05, S N 5 4 S 0 5 _ I OR W PACKAGE SN7405, SN74H05 . . . J OR N PACKAGE

IC 74273

Abstract: 74L8273 SNS4LS273 SN74LS273 V ls273
Contextual Info: TYPES SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR TTL MSI B U L L E T I N N O . O L-S 7 S 1 2 0 9 1 . O C T O B E R 1976 Contains Eight Ffip-Flops with Single-Rail Outputs SN M 273. SN B4LS273. . . J PA C KA G E SN74273. SN74LS273 . . . J OR N PA C KA G E

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

74170

Abstract: OF IC 74170
Contextual Info: TTL MSI TYPES SN54170, SN54LS170. SN74170, SN74LS170 4-BY-4 REGISTER FILES WITH OPEN-COLtECTOR OUTPUTS B U L L E T IN N O , D L -S 7 6 1 1 3 4 9 , M A R C H 1 9 7 4 — R E V IS E D O C T O B E R 1 9 7 6 • Separate Read/Write Addressing Permits Simultaneous Reading and Writing

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS M ARCH 1993 OB, DW, OR PW PACKAGE TOP VIEW • Space-Saving Package Option: Shrink Small-Outline Package (DB) Features EIAJ 0.65-mm Lead Pitch • EPIC (Enhanced-Performance Implanted

SN54LS628J

Contextual Info: SN54LS624 THRU SN54LS629, SN74LS624 THRU SN74LS629 VOLTAGE-CONTROLLED OSCILLATORS D 2 5 0 1 , JA N U A R Y 1 9 8 0 - REVISED M AR C H 1 9 9 8 Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Output Circuitry Highly Stable Operation over Specified

Contextual Info: I SN74LVC158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCAS342 - MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

74ls303

Abstract: 7459 IC TTL sn 7458 IC 7458 64LS 84ls IC 7459 IC 74283 sn 7457
Contextual Info: TTL MSI . TYPES SNS41S3I3. S1I74LS363 DUAL 4-LINE-TO-l-LHftf DATA SILECTOit^MULIU>LEXERS WITH 3-STATE OUTPUTS B U LLETIN NO. DL-S 781246J , O CTO BER 1976 SN 54LS 353 . . . J O R W P A C K A G E SN 74LS 353 . . . J O R N P A C K A G E T O P V |E W Inverting Versions of SN54LS253, SN74LS2S3

SN54LV14

Abstract: 2020CN
Contextual Info: SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS _ S C L S 1 8 7 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-|i Process SN54LV14 . . . J OR W PACKAGE SN74LV14. . . D, DB, OR PW PACKAGE (TOP VIEW) TVplcal V q l p (Output Ground Bounce)

Contextual Info: SN74LVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET JANUARY 1993 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted 1CCR [ 1 1D [ 2 CMOS) Submicron Process • 1CLK [ 3 Designed to Facilitate Incident Wave

Contextual Info: SN54LVU04, SN74LVU04 HEX INVERTERS S C L S 1 B 5 B - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)

Z62D

Contextual Info: TYPES SN54LS597, SN54LS598, SN74LS597, SN74LS598 8-BIT SHIFT REGISTERS WITH INPUT LATCHES 0 2 6 3 5 , J A N U A R Y 1 9 8 1 - R E V lS E D D E C E M B E R 1 9 8 3 S N 5 4 L S 5 9 7 . . . J PACKA GE S N 7 4 1 S 5 9 7 . . . J OR N PACKAGE 8 -B it Parallel Storage Register Inputs

54LS590

Abstract: ls590 w31140
Contextual Info: TYPES SN54LS590, SN54LS591, SN74LS590, SN74LS591 8-BIT BINARY COUNTERS WITH OUTPUT REGISTERS D2632, JANUARY 1961 - REVISED JUNE 1983 SN 54LS590, SN54LS591 . . . J OR W PACKAGE SN74LS590, SN74LS591 . . . J OR N PACKAGE 8-Bit Counter w ith Register Parallel Register Outputs

ge 31-155

Contextual Info: TYPES ¡'N54LS595, SN54LS596, SN74LS595, SNJ41S596 8-b. ' ^HIFT REGISTERS WITH OUTPUrDfRîtfES 0 2 6 3 4 , J A N U A R Y 1981 - 8-B it Serial -In, Parallel-Out Shift Registers w ith Storage R E V I S E D D E C E M B E R 1983 S N 54 LS 595 . S N 5 4 L S 5 9 6 . J OR W PA C KA G E